CHAPTER 1 : FLIP FLOP & COUNTERS

Chapter 1 : WEEK 3

Asynchronous counter
❑ Up-counter
❑ MOD counter
❑ Decade counter
Synchronous counter
❑ Up-counter
❑ Irregular binary counter
❑ Synchronous mod counter
❑ Up/down (bidirectional) synchronous counter
❑ Cascaded counter
❑ Decade counter & BCD counter
❑ Counter decoding
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Previous class: Asynchronous counter
Simple design
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Q0 Q1 Q2
J Q J Q J Q
CLK

K Q' K Q' K Q' 3-bit binary up counter

Q0 Q1 Q2
J Q J Q J Q
CLK

3-bit binary down counter

K Q' K Q' K Q'

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Synchronous counter
❑ Synchronous
◼ All flip-flops are simultaneously driven by common clock

2n = no. of states

n = no. of bits

◼ Each type of counter are classified by;

❑ Sequence i.e up or down
❑ Number of states i.e 2-bit will have 4 states (2N)
❑ Number of flip-flops i.e same as number of bits

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Synchronous counter (cont.)
◼ Also known as parallel counter.
◼ Synchronous counters eliminate the propagation delay problem
because all the clock inputs (cp) are tied to a common clock.
◼ Can operate at higher clock frequencies. Asynchronous counters
are not useful at very high frequencies, especially for large
number of bits.
◼ Requires more circuitry than the asynchronous counterpart.
◼ The design starts with
❑ State diagram
❑ Truth table
❑ K-map & equation
❑ circuit

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Excitation table

◼ The flip-flop inputs are based on excitation table.

Qt Qt+1 S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0

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Types of synchronous counter

◼ Up counter. Eg: 0→1→2→3

◼ Down counter. Eg: 3→2→1→0
◼ Irregular binary sequence counter. Eg:0→3→4→7
◼ Synchronous mod-counter
◼ Up/down counter or bidirectional counter (a control
input is required for selection of modes).
◼ Up counter or down counter with asynchronous
inputs (active high or active low preset and clear).

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Design step for synchronous up counter

Example: Design a 2 bit counter using D, T and

JK flip-flop based on the sequence 0→1→2→3.

Step 1: Draw the state diagram

00
0

11 3 1 01

10

8
Design step for synchronous up counter
(continue)
Step 2: Fill in the truth table PS
Q1 Q0
0 0
Present state Next state Flip-flop inputs
0
Q1 Q0 Q1 Q0 D1 D0 NS
0 0 0 1 0 1 3 1
Q1 Q0
0 1 1 0 1 0 Q1 Q0
0 1
1 0 1 1 1 1 1 1
2
1 1 0 0 0 0
Q1 Q0
1 0
# The flip-flop inputs are based on the excitation table
PS NS
- Ignore SR
Qt Qt+1 S R J K D T - D FF follows NS
0 0 0 X 0 X 0 0 - T FF toggles according to
0 1 1 0 1 X 1 1 bit change
1 0 0 1 X 1 0 1 - For JK FF, you need to
1 1 X 0 X 0 1 0 memorize the table

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Design step for synchronous up counter
(continue)
Step 3: Generate k-map

D1 = Q1.Q0'+Q1'.Q0 D0 = Q0'

Step 4: Draw logic circuit

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Up counter using T flip-flop

◼ Using T flip-flop
0

3 1

T1 = Q0 T0 = 1
Present state Next state Flip-flop inputs
Q1 Q0 Q1 Q0 T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1 VCC
1 1 0 0 1 1
T0 Q0 T1 Q1

Qt Qt+1 S R J K D T
0 0 0 X 0 X 0 0 Q0' Q1'
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1 CLK
1 1 X 0 X 0 1 0

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Up counter using JK flip-flop
◼ Using JK flip-flop
0

3 1
J1 = Q0 K1 = Q0

Present state Next state Flip-flop inputs

Q1 Q0 Q1 Q0 J1 K1 J0 K0
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X K0 = 1
J0 = 1
1 1 0 0 X 1 X 1 VCC

Qt Qt+1 S R J K D T J0 Q0 J1 Q1
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1 K0 Q0' K1 Q1'
1 1 X 0 X 0 1 0

CLK

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Design of Synchronous Counter Example 1

 Design a counter to produce 3-bit binary counter using J-K FF

 State diagram  State and excitation tables

PRESENT NEXT STATE FLIP-FLOP INPUTS

STATE
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
Qt Qt+1 S R J K D T 1 1 0 1 1 1 X 0 X 0 1 X
0 0 0 X 0 X 0 0
1 1 1 0 0 0 X 1 X 1 X 1
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0

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Design of Synchronous Counter Example 1 (continue..)

 Design a counter to produce 3-bit binary counter using J-K FF

 K-maps

J 0 = 1, K 0 = 1
J1 = Q0 , K1 = Q0
J 2 = Q1Q0 , K 2 = Q1Q0

 Counter implementation

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Design of Synchronous Counter Example 2

 Design a counter to produce 3-bit binary counter using D FF

 State diagram  State and excitation tables

PRESENT NEXT STATE FLIP-FLOP INPUTS

STATE
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
Qt Qt+1 S R J K D T 1 1 1 0 0 0 0 0 0
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0

D input follows NS

15
Design of Synchronous Counter Example 2 (continue..)

 Design a counter to produce 3-bit binary counter using D FF

 K-maps
Q0 Q0 Q0
Q 2Q 1 0 1 Q 2Q 1 0 1 Q 2Q 1 0 1
00 0 0 00 0 1 00 1 0

01 0 1 01 1 0 01 1 0

11 1 0 11 1 0 11 1 0

10 1 1 10 0 1 10 1 0

D2 map D1 map D0 map

D2 = Q2Q1Q0 + Q2 Q0 + Q2 Q1
D1 = Q1 Q0 + Q1Q0 = Q1  Q0
D0 = Q0

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Design of Synchronous Counter Example 2 (continue..)

 Design a counter to produce 3-bit binary counter using D FF

 Counter implementation

SET SET SET

D Q D Q D Q

Q Q Q
CLR CLR CLR

FF0
FF1 FF2
CLK

Q0 Q1 Q2

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Irregular Binary Counter
◼ Counting without according to regular sequence.
Eg: Design a counter with the irregular binary count
sequence 0→3→4→7 using D flip-flop.
◼ Answer:
D2 = Q2.Q0’+Q2’Q0
0
D1 = Q0’
7 3
D0 = Q1’

Present state Next state Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 1 1 0 1 1
0 0 1 X X X X X X
D0 Q0
0 1 0 X X X X X X D1 Q1 D2 Q2
0 1 1 1 0 0 1 0 0
1 0 0 1 1 1 1 1 1 Q0'
Q1' Q2'
1 0 1 X X X X X X
1 1 0 X X X X X X
1 1 1 0 0 0 0 0 0 CLK

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Synchronous mod-counter

◼ Example: Design a mod-5 synchronous

counter using D flip-flop. How many states
does this counter have? What is the minimum
number of flip-flop required?
◼ Answer: The counter will count from 0→4.
Therefore there are 5 states. 3 flip-flops are
required.

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Synchronous mod-counter (continue)
Present state Next state Flip-flop inputs
0 Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
4 1 0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
1 0 1 X X X X X X
3 2 1 1 0 X X X X X X
1 1 1 X X X X X X

D2 = Q1.Q0

D1 = Q1.Q0’+Q1’.Q0

D0 = Q2’.Q0’

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Design of Synchronous Counter Example 3

 Design MOD5 synchronous counter using D FF

 State diagram  State and excitation tables

PRESENT NEXT STATE FLIP-FLOP INPUTS

STATE
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0

21
Design of Synchronous Counter Example 3 (continue..)

 Design MOD5 synchronous counter using D FF

 K-maps
Q0 Q0 Q0
Q 2Q 1 0 1 Q 2Q 1 0 1 Q 2Q 1 0 1
00 0 0 00 0 1 00 1 0

01 0 1 01 1 0 01 1 0

11 0 0 11 0 0 11 0 0

10 0 0 10 0 0 10 0 0

D2 map D1 map D0 map

D2 = Q2Q1Q0
D1 = Q2 Q1Q0 + Q2Q1 Q0
D0 = Q2 Q0

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Design of Synchronous Counter Example 3 (continue..)

 Design MOD5 synchronous counter using D FF

 Counter implementation

SET SET SET

D Q D Q D Q

CLR
Q Q CLR
Q
CLR

FF0
FF1 FF2
CLK

Q0 Q1 Q2

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Design of Synchronous Counter Example 4

 Design MOD5 synchronous counter using T FF

 State diagram  State and excitation tables

PRESENT NEXT STATE FLIP-FLOP INPUTS

STATE
Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 0 0 0 1 0 0
1 0 1 0 0 0 1 0 1
1 1 0 0 0 0 1 1 0
1 1 1 0 0 0 1 1 1

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Design of Synchronous Counter Example 4 (continue..)

 Design MOD5 synchronous counter using T FF

 K-maps
Q0 Q0 Q0
Q 2Q 1 0 1 Q 2Q 1 0 1 Q 2Q 1 0 1
00 0 0 00 0 1 00 1 1

01 0 1 01 0 1 01 1 1

11 1 1 11 1 1 11 0 1

10 1 1 10 0 0 10 0 1

T2 map T1 map T0 map

T2 = Q2 + Q1Q0
T1 = Q2Q0 + Q2Q1 + Q1Q0
T0 = Q2 + Q0

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Design of Synchronous Counter Example 4 (continue..)

 Design MOD5 synchronous counter using T FF

 Counter implementation

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Up/Down Synchronous Counter (bidirectional counter)

• Bidirectional counters, also referred to as UP/DOWN counters, are capable

of progressing in either direction through any given count sequence. Recall
that in general, bidirectional counters can be reversed at any point in their
count sequence.
• Capable to count in either direction through a certain sequence
• For example 3-bit up/down synchronous counter
 Able to count from 0 to 7 or 7 to 0

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Up/Down Synchronous Counter design procedure

◼ Eg: Design a 2 bit up/down counter using T flip-flop based on the

state diagram below. Assume up = 1 and down = 0.
Answer:
1 0 1

0 0
3 1
0 0

1
2 1

Present state Next state Y Flip-flop inputs

Q1 Q0 Q1 Q0 up = 1 T1 T0
down = 0
0 0 1 1 0 1 1
0 0 0 1 1 0 1
0 1 0 0 0 0 1
0 1 1 0 1 1 1
1 0 0 1 0 1 1
1 0 1 1 1 0 1
1 1 1 0 0 0 1
1 1 0 0 1 1 1

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Cascaded Counters
• Counters can be connected to achieve higher modulus
operation.

• Cascading means that the last stage output of one counter

drives the input of the next counter.

• A mod-M and a mod-N counter in cascade give a mod-MN

counter.

• 2 types of cascading: Asynchronous cascading and

synchronous cascading

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Cascaded Counters (continue)
Asynchronous cascading
Two asynchronous counters connected in cascade for a 2 bit and a
3 bit ripple counter. The overall modulus of the two cascaded
counters is 4 x 8 = 32; that is they act as a divide-by-32 counter.

2 3

CLK MOD-4 MOD-8

→ Not practical due to propagation delay

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Cascaded Counters (continue)
Synchronous cascading
◼ In synchronous cascaded counter, it is necessary to use the count enable
(CTEN) and the terminal count (TC) functions to achieve higher modulus
operation.
◼ Terminal count (TC) is analogous to ripple clock or ripple carry out (RCO)
on some IC counters.

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Cascaded Counters (continue)
◼ Example 1: The figure below shows a mod-10 counter
and mod-8 counter connected in cascade. What is the
overall modulus of these two cascaded counter?
Determine the frequency at B if fin is 20kHz.

Answer:
Overall modulus = 10 x 8 =80 = mod-80 counter
Frequency at B = fin/80 = 250Hz

•32
Cascaded Counters (continue)

◼ Example 2:
How many decade counters are required to convert a clock of 1
MHz to 1 Hz? Draw the circuit.
Answer: fout = fin/10n

1 = (1x106)/10n
n = log (1x106)/log10
n = 6 decade counter

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Cascaded Counters (continue)

Example 3: Determine the overall modulus of the two cascaded

counter for (a) and (b)

Answer:
(a) the overall modulus for the 3 counter configuration is 8 x 12 x 16
= 1536 = mod-1536
(b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x
5 = 1400 = mod-1400

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Decade Counters/BCD counters

◼ Decade counter
❑ Any counter has 10 distinct states, no matter what
the sequence.

◼ BCD counter
❑ A decade counter counts in sequence from
0000(zero) through 1001(decimal 9).

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Counter Decoding (decoding a counter)

◼ Decoding of the counter is needed to determine the

current binary states in its sequence. Decoders or logic
gates can be used to decode the current state.
1. Active-High Decoding (AND gate)
2. Active-Low Decoding (NAND gate)
3. BCD counter decoding

36
Counter Decoding (decoding a counter)
Example: A 3-bit counter with active-HIGH decoding of count 2 and count 7.

0 1

1 1
0 1

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Decoding glitches
◼ The decoding process of synchronous counter may also resort to
glitches.
◼ Due to propagation delay from the clock to the Q output of every
flip-flop

glitch

◼ What is glitch? Glitch is an erroneous count patterns or unwanted

output voltage caused by the propagation delay effect.

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Example of glitches

0 1 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0 0 0

0 0 0 0 1 1 1 1 0 0 0

0 0 0 0 0 0 0 0 1 1 0

Figure: a MOD-10 counter

connected to a decoder

Figure: The glitch can be seen at

You can connect the decoder to a the outputs of decoder
7-segment display to know the
decimal sequence

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Solution to eliminate glitches
◼ Strobing - enable the decoder decodes outputs at a time after the
glitches have had time to disappear.
◼ Accomplished in the case of an active high clock by using the low
level of the clock to enable the decoder.
◼ Strobing is a technique applied to circuits receiving the output of
an asynchronous (ripple) counter, so that the false counts
generated during the ripple time will have no ill effect.
❑ Essentially, the enable input of such a circuit is connected to the counter's
clock pulse in such a way that it is enabled only when the counter outputs
are not changing, and will be disabled during those periods of changing
counter outputs where ripple occurs.

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Example without glitches

Figure: the basic decade counter

and decoder to with strobing to
eliminate glitches
Figure: Strobed decoder outputs

41
Exercise 1
◼ Design a 3 bit up/down counter using JK flip-flop based on the
state diagram below. Assume up = 1 and down = 0.

0
0 0
1
7 1
1
0
0
1
1

6 2
1 1
0
0

5 1
1 3

0 4 0

42
Exercise 2

Design a 3 bit synchronous counter for the

sequence 0→6→4→2 using
a) D flip-flop
b) T flip-flop
c) JK flip-flop

43
Exercise 3
◼ Design synchronous counters that goes
through the shown states (use JK flip flops).
Assume that state 111 and 011 are unused
state. Test the unused state to not block the
system

44
Answer

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