CHAPTER 1 : FLIP FLOP & COUNTERS

Chapter 1 : WEEK 2

Asynchronous counter
❑ Up-counter
❑ MOD counter
❑ Decade counter
Synchronous counter
❑ Up-counter
❑ Irregular binary counter
❑ Synchronous mod counter
❑ Up/down (bidirectional) synchronous counter
❑ Cascaded counter
❑ Decade counter & BCD counter
❑ Counter decoding

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Introduction

Counter
◼ A counter is a type of sequential logic circuit consisting of a set of flip-
flops which can go through a sequence of states.
◼ Its function is to count the input pulses (clock signal) and store the
result till the arrival of the next signal.
◼ The counting process, therefore consists of a series of storage and
addition operations.
◼ The counters are built from flip-flops and of gate circuits.

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 Counters

Asynchronous counter Synchronous counters

(Ripple counter) Clock pulse is applied to
each FF simultaneously
The output of one FF drives
the input of the next one

High Speed
Slow speed

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Classification of counters (cont.)
◼ According to the direction of counting:
❑ up counter
❑ down counter
❑ Up-down counter

◼ According to state encoding:

❑ binary
❑ decade (e.g. BCD)
❑ others
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 States of a counter
◼ The state transition diagram of
counters is of the form of a
closed ring.
❑ Example: mod 6 counter
◼ The number of states, the
counter goes through before
recycling is the modulus of the
counter.
◼ The largest possible modulus of
a n-bit counter is 2n.

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Introduction (continue)

◼ Counters are formed by connecting flip-flops

together
◼ Types of counter are;
❑ Asynchronous
◼ Also known as ripple counter
◼ The first flip-flop is driven by external clock while the
successive flip-flops by the output of preceding flip-flop

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Asynchronous counter
◼ Also known as ripple counter. Ripple counters are the
simplest type of binary counters because they require
the fewest components to produce a given counting
operation.
◼ Each FF output drives the CLK input of the next FF.
◼ FFs do not change states in exact synchronism with the
applied clock pulses.
◼ There is delay between the responses of successive
FFs.
◼ It is also often referred to as a ripple counter due to the
way the FFs respond one after another in a kind of
rippling effect.

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Up counter and down counter for negative
edge clock
1

Q0 Q1 Q2
J Q J Q J Q
CLK

K Q' K Q' K Q' 3-bit binary up counter

Q0 Q1 Q2
J Q J Q J Q
CLK

3-bit binary down counter

K Q' K Q' K Q'

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Up counter and down counter for positive
edge clock
1

Q0 Q1 Q2
J Q J Q J Q
CLK

K Q' K Q' K Q' 3-bit binary down counter

Q0 Q1 Q2
J Q J Q J Q
CLK

3-bit binary up counter

K Q' K Q' K Q'

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Asynchronous Counter Operation

 For example, 2-bit asynchronous binary counter using J-K FF

 CLK is only connected to 1st FF0, LSB FF

Is this FF an up
 The 2nd FF clock is driven by Q0 of 1st FF counter or down
 Both FF input are always HIGH counter?
 Q0 changes state at the positive-edge clock Which FF is MSB?
 Q1 change at the positive-edge of the Q0
 Note that the two FFs do not triggered at the same time because clock and
Q0 transitions do not occur at the same time

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Asynchronous Counter Operation (continue..)

 Timing diagram for 2-bit asynchronous binary counter

0 1 0 1 0
0 0 1 1 0

 Four clock pulses are applied, assume initially all LOW

 Q0 (LSB) is always toggle at positive-edge clock (J and K are HIGH)
 Q0 is reciprocal of Q0
 Q1(MSB) is toggle at positive-edge of Q0
 At 4th clock pulse, the counter is recycle to its original state (both FF are
LOW)

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Asynchronous Counter Operation (continue..)

 Binary state sequence for 2-bit asynchronous binary counter

 The counter is in up sequence (Q1 is MSB, Q0 is LSB)

 Count from 0 to 3 in binary sequence
 The term ‘recycle’ refers to the transition from final state to original state
 Therefore, 2-bit asynchronous counter has four state and consists of two FF

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A 3-bit Asynchronous Binary Counter

 Draw 3-bit asynchronous counter using J-K FFs

Is this FF an up
counter or down
counter?

Which FF is MSB?

 Sketch the timing diagram for 3-bit asynchronous up counter

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A 3-bit Asynchronous Binary Counter (continue..)

 Tabulate the state sequence for 3-bit asynchronous up counter

 Conclusion, 3-bit asynchronous up counter consists of three J-K FFs and

counts from 0 to 7 (8 states)

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Disadvantages of asynchronous counter: Propagation Delay

 Propagation delay in 3-bit asynchronous counter (ripple clocked) binary

counter as shown below

 Propagation delay occurs through FF0 cause Q0 lags some time compare to CLK
 This effect ‘ripples’ the next FF resulting Q1 delay some time from Q0
 The cumulative delay of asynchronous counter is the major disadvantage of this
counter in many applications.
 It limits the rate at which the counter can be clocked and creates decoding problems.
 The maximum cumulative delay in a counter must be less than the period of the clk
waveform.

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Disadvantages of asynchronous
counter (continue)
◼ Asynchronous counters are not useful at very
high frequencies, especially for counters with
large number of bits.
◼ Another problem caused by propagation
delays in asynchronous counters occurs
when we try to electronically detect (decode)
the counter’s output states.

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Disadvantages of asynchronous
counter (continue)
◼ Eg: If you look closely at the figure below, for a short period of time (50ns) right after state 011,
you see that state 010 occurs before 100.
◼ This is obviously not the correct binary counting sequence and while the human eye is much too
slow to see this temporary state, our digital circuits will be fast enough to detect it.
◼ These erroneous count patterns can generate what are called glitches in the signals that are
produced by digital systems using asynchronous counters. In spite of their simplicity, these
problems limit the usefulness of asynchronous counters in digital applications.

glitch

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Exercise: A 4-bit Asynchronous Binary Counter

 Draw the timing diagram for 4-bit asynchronous up counter given below

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A 4-bit Asynchronous Binary Counter (Continue)

◼ Each flip-flop has a propagation delay for 10ns. Determine the total propagation
delay time from the triggering edge of a clock pulse until a corresponding
change can occur in the state of Q3. Also determine the maximum clock
frequency at which the counter can be operated.

Answer:
For the total delay time, the effect of CLK8 or CLK16 must propagate through 4
flip-flops before Q3 changes.

tp(tot) = 4 x 10ns = 40ns

The maximum clock frequency is

fmax = 1/tp(tot) = 1/40ns = 25MHz

* The counter should be operated below this frequency to avoid problems due to
the propagation delay.

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Asynchronous MOD counter
◼ MOD number is generally equal to the number
of states that the counter goes through in each
complete cycle before it recycles back to its
starting state.
◼ MOD number can be increased simply by
adding more FFs to counter. MOD number = 2N
◼ The 2-bit ripple counter is called as MOD-4
counter and 3-bit ripple counter is called as
MOD-8 counter. So in general, an n-bit ripple
counter is called as modulo-N counter. Where,
MOD number = 2n.
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Asynchronous MOD counter (cont.)
◼ Example
❑ A photocell and light source combination is used
to generate a single pulse each time an item
crosses its path. The counter must be able to
count as many as 1000 items. How many FFs are
required?
ans.)
2n = 1000
n = log1000/log2
= 10 FFs
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Asynchronous MOD counter (cont.)
◼ Type of modulus:
❑ 2-bit up or down (MOD-4)
❑ 3-bit up or down (MOD-8)
Full sequence
❑ 4-bit up or down (MOD-16) counter
→ Ideal for use in frequency division

◼ But it is also possible to use the basic asynchronous

counter to construct special counters with counting
states less than their maximum output number.
◼ a n-bit counter whose modulus is less than the
maximum possible is called a truncated counter.

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Asynchronous MOD counter (cont.)
◼ We can create truncated counter using
combinational logic gates.
◼ Eg: We can take the modulo-16 (4 FFs)
asynchronous counter and modified it with
additional logic gates it can be made to give a
decade (divide-by-10) counter output for use
in standard decimal counting and arithmetic
circuits.

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Asynchronous Decade Counter (BCD counter/MOD-10 counter)
 Counters can be designed to have a number of states in their sequence that
is less than the maximum of 2N. This type of sequence is called a truncated
sequence.
 For example, asynchronous modulus ten (MOD-10) counter or decade
counter Partial
decoding
0 1 0 1

 NAND gate inputs are derived from Q3 AND Q1

 Note that 10 is 1010 which is Q3 AND Q1 are HIGH 1010 = 10102
MSB LSB
 CLR is produced and then reset all FFs to recycle
 The counter count again

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Asynchronous Decade Counter (continue..)
 Timing diagram and binary state sequence for decade counter

• The reason for this glitch is that Q1 must first go HIGH

before the count of ten can be decoded.
• Not until several nanoseconds after the counter goes to the
count of ten, the output of the decoding gate goes LOW
(both inputs are HIGH).
• Thus, the counter is in the 1010 state for a short time before
it is reset to 0000, thus producing the glitch on Q1 and the
resulting glitch on the CLR’ line that reset the counter.

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Frequency Division

◼ Each flip-flop provides an output waveform

that is exactly half the frequency of the
waveform at its CLK input.
◼ In any counter, the signal at the output of the
last flip-flop (i.e; the MSB) will have a
frequency equal to the input clock frequency
divided by the MOD number of the counter.

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Frequency Division (continue)
◼ E.g: in a MOD-16 counter, the output from the last FF
will have a frequency of 1/16 of the input clock
frequency. Thus, it can also be called a divide-by-16
counter. Likewise, a MOD-8 counter has an output
frequency of 1/8 the input frequency; it is a divide-by-8
counter.

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 Example

60-Hz signal is fed into a Schmitt-trigger, pulse-shaping circuit

to produce a square wave.
60Hz square wave is then put into a MOD-60 counter, which
is used to divide the 60-Hz frequency by exactly 60 to produce
a 1-Hz waveform.
1-Hz waveform is fed to a series of counters, which then count
Ss, Ms, Hs, and so on. How many FFs are required for the
MOD-60 counter?
26 = 64, so MOD-60 = 6 FFs

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 Example: MOD counter
Determine the MOD number of the counter in the figure
below. Also determine the frequency at the D output.

Step 1: Determine which

1 1 1 0 FF is LSB and MSB
Step 2: Identify which FF
output that produces “1”
Step 3: Convert the FF
connections from binary
MSB LSB
to decimal 11102 = 1410

Ans.) Mod-14 ripple counter, 30/14 = 2.14 kHz

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Example: MOD counter (cont.)
The MOD-10 counter below will count from 0000 through
1001. Determine the frequency at the D output.

Ans.) 1M/10 = 0.1Hz

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Exercise (cont.)

1. Design the circuit for asynchronous counter

according to these characteristics:
❑ MOD 13 counter using JK flip-flops.
❑ Negative edge triggered
❑ Down counter
❑ Active low preset and clear input

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Answer:

1
0 1 0 0
Q0 Q1 Q2 Q3
J CLR Q J CLR Q J CLR Q J CLR Q
CLK

K PRE
Q' K PRE
Q' K PRE Q' K PRE Q'

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