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Vlsi Course-Physical Design

The 3 month program covers VLSI design flow from RTL coding through FPGA board bring up. It includes classes taught by industry experts on topics such as architecture specifications, RTL coding, synthesis, DFT, floorplanning, power planning, clock tree synthesis, timing optimizations, routing, LVS/DRC, ATPG, gate-level simulation, static timing analysis, GDSII generation, low power techniques, multi-mode multi-corner timing analysis, and design for yield and manufacturability. The program aims to provide skills useful for jobs, higher education, and career growth in fields like VLSI engineering and university teaching.

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Mahesh Kanike
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95 views2 pages

Vlsi Course-Physical Design

The 3 month program covers VLSI design flow from RTL coding through FPGA board bring up. It includes classes taught by industry experts on topics such as architecture specifications, RTL coding, synthesis, DFT, floorplanning, power planning, clock tree synthesis, timing optimizations, routing, LVS/DRC, ATPG, gate-level simulation, static timing analysis, GDSII generation, low power techniques, multi-mode multi-corner timing analysis, and design for yield and manufacturability. The program aims to provide skills useful for jobs, higher education, and career growth in fields like VLSI engineering and university teaching.

Uploaded by

Mahesh Kanike
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dear Student, 1) Orientation program for 2 hours covering basic VLSI design flow, various applications involving chip

design, how the course will be useful for getting jobs, higher education (MS/M.Tech), career and knowledge growth in professions such as VLSI engineer, university lecturer/professor.

PROGRAM DETAILS :
The program covers classes taken by industry experts and exercises carefully monitored by experts. Program will also cover in detail FPGA flow from RTL coding till board bring up. Total program Duration: 3 months

CONTENTS IN BRIEF:Architecture Specifications : Area, Power, Timing, Functionality, PVT .

RTL Coding:

VHDL concepts, Verilog concepts, Interview questions, RTL Guidelines for effective coding and synthesis.

Synthesis:

Standard design constraints, Netlist Generation.

DFT:

Scan insertion, Controllability and Observability.

FloorPlanning :

Techniques, Hard macro Placement, Thermal and Mechanical Effects

PowerPlanning:

Power routing.

Clock Tree Synthesis:

Clock Buffering, Clock skew and Clock latency.

Timing Optimizations:

Cloning, Buffering, Switching to higher metal layers, Removing un-used logic, constant propagation.

Routing:

Interconnects, Cross talk delay and cross-talk noise.

LVS/DRC:

Layout Vs Schematic and Design Rule Checks, Advanced DRC routing rules for deep sub-micron technology nodes like 45nm and 28nm.

ATPG :

Automatic Test Pattern Generation

Gate-Level Simulation :

Asynchronous path checks, Test benches for important Complex functional and timing checks.

Static Timing Analysis:

Setup and Hold Analysis, False and Multi-Cycle paths, On Chip Variation, Statistical Static Timing Analysis.

GDSII generation :

Understanding fab requirements, various fabrication units. Low power VLSI covering various industry standard low power techniques targeted for leakage and dynamic power optimization. Mulit-mode Multi-corner timing analysis and optimization.

Design For Yield and Manufacturability (DFM and DFY).

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