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DSD_Lab_Solutions

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3 views

DSD_Lab_Solutions

Uploaded by

keatsjohn562
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System Design Solutions

1. Random Sequence Generator with 7-Segment Selector

Part A:

Verilog Code:

module random_sequence_generator(

input wire clk,

input wire reset,

input wire enable,

input wire switch,

output reg [3:0] seq_out,

output reg [6:0] display

);

reg [1:0] counter = 0;

always @(posedge clk or posedge reset) begin

if (reset)

counter <= 0;

else if (enable)

counter <= counter + 1;

end

always @(*) begin

case (counter)

2'd0: seq_out = 4'd0;


2'd1: seq_out = 4'd1;

2'd2: seq_out = 4'd5;

2'd3: seq_out = 4'd7;

endcase

display = (switch) ? seq_out : seq_out; // Set up your 7-segment logic here.

end

endmodule

Part B:

Testbench:

module testbench;

reg clk, reset, enable, switch;

wire [3:0] seq_out;

wire [6:0] display;

random_sequence_generator uut(

.clk(clk),

.reset(reset),

.enable(enable),

.switch(switch),

.seq_out(seq_out),

.display(display)

);

initial begin

clk = 0; reset = 1; enable = 0; switch = 0;


#10 reset = 0;

#10 enable = 1;

#50 switch = 1;

end

always #5 clk = ~clk; // Clock generator

endmodule

2. 4-bit Up/Down Counter with Selectable Output

Part A:

Verilog Code:

module up_down_counter(

input wire clk,

input wire reset,

input wire enable,

input wire up_down, // 1 for up, 0 for down

input wire display_select, // 1 for 7-segment, 0 for LEDs

output reg [3:0] count,

output reg [6:0] display

);

always @(posedge clk or posedge reset) begin

if (reset)

count <= 0;

else if (enable) begin


if (up_down)

count <= count + 1;

else

count <= count - 1;

end

end

// 7-segment display logic to be added here

endmodule

Part B:

Testbench:

module testbench;

reg clk, reset, enable, up_down, display_select;

wire [3:0] count;

wire [6:0] display;

up_down_counter uut(

.clk(clk),

.reset(reset),

.enable(enable),

.up_down(up_down),

.display_select(display_select),

.count(count),

.display(display)

);
initial begin

clk = 0; reset = 1; enable = 0; up_down = 1; display_select = 0;

#10 reset = 0;

#10 enable = 1;

#50 up_down = 0; display_select = 1;

end

always #5 clk = ~clk; // Clock generator

endmodule

3. Modulo-6 Counter with Select Line

Part A:

Verilog Code:

module modulo_6_counter(

input wire clk,

input wire reset,

input wire select,

output reg [2:0] count,

output reg [5:0] led

);

always @(posedge clk or posedge reset) begin

if (reset)

count <= 0;

else if (count == 5)
count <= 0;

else

count <= count + 1;

end

always @(*) begin

led = (select) ? {3'b000, count} : {count, 3'b000};

end

endmodule

Part B:

Testbench:

module testbench;

reg clk, reset, select;

wire [2:0] count;

wire [5:0] led;

modulo_6_counter uut(

.clk(clk),

.reset(reset),

.select(select),

.count(count),

.led(led)

);

initial begin
clk = 0; reset = 1; select = 0;

#10 reset = 0;

#10 select = 1;

end

always #5 clk = ~clk; // Clock generator

endmodule

4. Random Sequence with Push Button Trigger and Clock Division

Part A:

Verilog Code:

module random_sequence_push(

input wire clk,

input wire reset,

input wire button,

output reg [3:0] seq_out

);

reg [1:0] counter;

reg slow_clk;

// Simple clock divider

always @(posedge clk or posedge reset) begin

if (reset)

slow_clk <= 0;

else
slow_clk <= ~slow_clk;

end

always @(posedge slow_clk or posedge reset) begin

if (reset)

counter <= 0;

else if (button)

counter <= counter + 1;

end

always @(*) begin

case (counter)

2'd0: seq_out = 4'd1;

2'd1: seq_out = 4'd2;

2'd2: seq_out = 4'd4;

2'd3: seq_out = 4'd7;

endcase

end

endmodule

Part B:

Testbench:

module testbench;

reg clk, reset, button;

wire [3:0] seq_out;


random_sequence_push uut(

.clk(clk),

.reset(reset),

.button(button),

.seq_out(seq_out)

);

initial begin

clk = 0; reset = 1; button = 0;

#10 reset = 0;

#10 button = 1;

#10 button = 0;

#20 button = 1;

end

always #5 clk = ~clk; // Clock generator

endmodule

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