EEE 3101: Digital Logic and Circuits

HDL

Course Teacher: Nafiz Ahmed Chisty

Associate Professor and Head (UG)

Department of EEE
Faculty of Engineering, AIUB
Room# DNG03, Ground Floor, D Building
Email: [email protected]
Website: http://engg.aiub.edu/
Website: www.nachisty.com
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Hardware Description Languages (HDL)

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Hardware Description Languages (HDL) allows designers to describe both behavior

(what does the circuit do functionally) and structure (how it is constructed from
smaller sub-systems) of a digital logic circuits, which can be verified by an HDL
simulator.
• Note that HDL languages describe hardware, not any instructions (programs) for
hardware.
• HDL languages execute code-segments (processes) in parallel.

• On the other hand, programming languages, which are used to instruct/program

microprocessors/microcontrollers, execute statements serially (one after another).

• Hardware blocks have no relative precedence, no one block is more or less important
in terms of when to activate. A block does not wait for another block to finish
computation to “turn on”. They all have to operate at the same time regardless of the
fact that some will receive inputs earlier and some will receive them later.

• The 3 standard HDL languages are

• Verilog HDL (IEEE standard 1364)
• VHDL (IEEE Standard 1076)
• SystemVerilog (IEEE Standard 1800)
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Electronic Design Automation (EDA)

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• Electronic Design Automation (EDA) tools automates various stages of the design process for
digital circuits.
• EDA tools allow HDL descriptions written at Register Transfer Level (RTL) to be realized in
hardware through certain automated steps such as Logic Synthesis and Place and Route
(PnR).
RTL Modeling
• All digital design are now described at Register Transfer Level (RTL) with an HDL language
first. This description is largely behavioral. In other words, here, sub-systems are generally
modeled behaviorally using control structures such as if and case structures and arithmetic
operators such as +, - for combinational logic and clock-edge-sensitive code for sequential
logic.
Logic Synthesis
• The verified HDL code is then taken through logic synthesis that automatically translates this
description into a more detailed gate-level description utilizing available logic cells of selected
technology library.
Place and Route (PnR)
• After the synthesized gate-level description is ready, it is automatically placed in the layout of
the chosen target chip/IC and then the interconnections between sub-systems are routed.
Device Configuration or Fabrication
• Note that after PnR, the layout is either configured on a fully-fabricated (but reconfigurable)
Field Programmable Logic Device (FPLD)* or sent to fabrication to be fabricated as an
Application Specific Integrated Circuit (ASIC).
• *such as a Field Programmable Gate Array (FPGA)
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

The Inverter
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Functional Simulation of the Verilog HDL code:

Verilog HDL code:
module my_not (input wire A,
output wire Y);
not (Y, A);
endmodule

The AND Gate

Verilog HDL code : Functional Simulation of the Verilog HDL code:
module and_2_to_1 (input wire A, B,
output wire Y);
and (Y, A, B);
endmodule

The OR Gate
Verilog HDL code : Functional Simulation of the Verilog HDL code:
module or_2_to_1 (input wire A, B,
output wire Y);
or (Y, A, B);
endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

The NAND Gate

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Verilog HDL code : Functional Simulation of the Verilog HDL code:

module nand_2_to_1 (input wire A, B,
output wire Y);
nand (Y, A, B);
endmodule

The NOR Gate

Verilog HDL code : Functional Simulation of the Verilog HDL code:
module nor_2_to_1 (input wire A, B,
output wire Y);
nor (Y, A, B);
endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Exclusive-OR Gate
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Verilog HDL code : Functional Simulation of the Verilog HDL code:

module xor_2_to_1 (input wire A, B,
output wire Y);
xor (Y, A, B);
endmodule

Exclusive-NOR Gate
Verilog HDL code : Functional Simulation of the Verilog HDL code:
module xnor_2_to_1 (input wire A, B,
output wire Y);
xnor (Y, A, B);
endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Verilog Logical Operators and Gate Primitive (pre-defined gates)

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Logical Function Gate Primitives Logical (Boolean) Operators

not/inversion/complementation not ~
and and &
or or |
xor/exor xor ^
nand nand ~&
nor nor ~|
xnor/exnor xnor ~^
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Chain vs Tree structure

• Consider a logical operation with 4 variables. F = A . B. C .D.
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

Each gate has a delay of 1 unit. Compute output delay of each case.

A module and_chain(input wire A, B, C, D,

output wire F);
B
F
C assign F = ( ( (A & B) & C) & D);
D
Chain
endmodule

A
module and_tree(input wire A, B, C, D,
B
output wire F);
F
assign F = (A & B) & (C & D);
C
endmodule
D
Tree
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Verilog HDL code for the “original” and “bubble-pushed” circuits

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

A P A
F P F
S S

Sbar Q Sbar Q
B B

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 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

The Half-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• 𝑆 = 𝐴̅. B + A. 𝐵̅= A⊕B

• COUT =A . B

//Device name and I/O ports

module HA (input wire A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B;
assign Cout= A & B;

endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

The Full-Adder
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

S = A ̅B̅CIN+ A̅BCIN + AB̅ CIN + ABCIN = A ⊕ B ⊕ C

C OUT = A̅BCIN+ AB̅CIN + ABCIN + ABCIN = AB +(A ⊕ B )C IN

//Device name and I/O ports

module FA(input wire Cin, A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B ^ Cin;
assign Cout= (A & B) | ((A ^ B ) & Cin);

endmodule
 Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Multi-bit AddersfromFull Adders

Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB

• A 2-bit adder can be constructed by cascading (series placement) of two full adders.
//Top-Level module
//Device name and I/O ports
module Adder_2Bit (input wire [1:0] A, B,
output wire [1:0] S,
output wire Cout);
//Define internal C incorporating all carry type signals
wire [2:0] C;
assign C[0] = 0; //Use C[0] just for a “symmetric look”

//Level-2
//Device name and I/O ports
module FA (input wire Cin, A, B,
output wire S, Cout);
//Define behavior/structure of the circuit
assign S= A ^ B ^ Cin;
assign Cout= (A & B) | ((A ^ B ) & Cin);
endmodule

//Define behavior/structure of the circuit

//Instantiating two half adders
FA FA1 (.Cin(C[0]), .A(A[0]), .B(B[0]), .S (S[0]), .Cout (C[1]));
FA FA2 (.Cin(C[1]), .A(A[1]), .B(B[1]), .S (S[1]), .Cout (C[2]));
assign Cout = C[2]; //Pass C[2] as Cout
endmodule
Nafiz Ahmed Chisty| Head (UG) and Associate Professor, Dept. of EEE, FE, AIUB Nafiz Ahmed Chisty| Associate Professor and Head (UG), Dept. of EEE, FE, AIUB| [email protected]

Reference:
[1] Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall.
[2] M. Morris Mano, “Digital Logic & Computer Design” Prentice Hall.

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Thanks