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Sheet - Logical Effort

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88 views4 pages

Sheet - Logical Effort

Uploaded by

beter.osama21
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Logical-Effort Method

Unless otherwise specified, adopt the following assumptions in the following


problems:
1. The mobility of the free electrons is twice that of the holes.
2. The aspect ratio of the NMOS device of the inverter is unity.

1. Define the logical effort, the electrical effort, and the parasitic delay.
2. Draw the relationship between the normalized delay and the electrical ef-
fort for 4-input NAND gate and 4-input NOR gate. Comment with a suita-
ble comparison between the two plots.
3. Evaluate the absolute delay of a 2-input NOR gate in the 65-nm CMOS
technology whose time constant is 3 ps. Assume the fan-out is 5.
4. Evaluate the logical effort and the parasitic delay of n-input NAND and
NOR gates in terms of n.
5. Sketch a 4-input NAND gate with transistor widths chosen to achieve
equal rise and fall times as that of a unit inverter. Show why the logical ef-
fort is 2.
6. A 4x inverter is one that has both its NMOS and PMOS transistors with
four times the size of those of a unit inverter. Find the input capacitance,
the logical effort, and the parasitic delay of this inverter.
7. Estimate the frequency of oscillation of a 7-stage ring oscillator fabricated
in the 65-nm CMOS technology with τ = 3 ps.
8. A path consists of an inverter, 2-input NAND gate, 3-input NOR gate, and
an inverter. Estimate the path logical effort and the path parasitic delay.
9. Estimate the minimum delay of the path from A to B in the figure below
and choose transistor sizes to achieve this delay. The initial NAND2 gate
presents a load of 8C on the input and the output load is equivalent to
45C.

1
10. Repeat Problem 9 with the second stage containing two 3-inputs NAND
gates and the third stage containing three 2-inputs NOR gates. Assume
that both the input and output capacitances remain the same.
11. Consider the two designs of a 2-input AND gate shown in the figure be-
low. Give an intuitive argument about which will be faster. Back up your
argument with a calculation of the path effort, delay, and input capaci-
tances, x and y, to achieve this delay.

12. Consider four designs of a 6-input AND gate shown in the figure below.
Develop an expression for the delay of each path if the path electrical ef-
fort is H. What design is fastest for H = 1? For H = 5? For H = 20? Explain
your conclusions intuitively.

13. Consider a process in which PMOS transistors have three times the effec-
tive resistance as that of the NMOS transistors. A unit inverter with equal
rising and falling delays in this process is shown in the figure below. Cal-
culate the logical efforts of a 2-input NAND gate and a 2-input NOR gate if
they are designed with equal rising and falling delays.
2
14. Generalize Problem 13 if the PMOS transistors have µ times the effective
resistance of NMOS transistors with the same dimensions. Find a general
expression for the logical efforts of a k-input NAND gate and a k-input
NOR gate in terms of µ. As µ increases, comment on the relative desirabil-
ity of NANDs versus NORs.
15. For a chain consisting of N inverters in cascade with a load capacitance of
64C and an input capacitance equal to C.
(a) Derive the expression of the path delay as a function of N.
(b) Plot the path delay of the chain for N ranging from 1 to 5.
(c) Comment on the resulting plot.
16. An output pad contains a chain of successively larger inverters to drive a
relatively enormous off-chip load capacitance. If the first inverter in the
chain has an input capacitance of 20 fF and the off-chip load is 10 pF, how
many inverters should be used to drive the load with least delay?
17. The clock buffer in the figure below can present a maximum input capaci-
tance of 100 fF. Both true and complementary outputs must drive loads of
300 fF. Compute the input capacitance of each inverter to minimize the
worst-case delay from input to either output. Assume that the inverter
parasitic delay is 1.

18. The clock buffer of Problem 17 is an example of a 1–2 fork. In general, if a

3
1–2 fork has a maximum input capacitance of C1 and each of the two legs
drives a load of C2, what should the capacitance of each inverter be and
how fast will the circuit operate? Express your answer in terms of pinv, C1,
and C2.
19. Derive the expression of the best stage effort that corresponds to the
least path delay for a logic gate consisting of n1 stages with path effort, F,
cascaded by N – n1 inverters.
20. Discuss the limitations of the logical-effort method for estimating the de-
lay.

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