School of Electrical & Electronic Engineering

IE2104 Digital Electronics

Academic Year 2024-2025

L2104A
Combinational Logic Circuits
Project Lab (S2-B4a-02)

Dress Code in the Laboratory

• Work shirt that covers the upper torso and arms.
• Lower body clothing that covers the entire leg.
• Closed-toe shoes that cover the top of the foot.

Please access this link:

https://ntu.sg/eee-EEEStudentCAGuidelines or scan the QR code below to access APO CA Guidelines.
The procedure to request for MAKE-UP LAB SESSION is on last page.

Laboratory Manual
1. Introduction
The basic logic gates perform basic Boolean functions such as AND, OR, NAND, NOR, Inversion (NOT),
Exclusive-OR (XOR), and Exclusive-NOR (XNOR). They are the essential building blocks of more complex
digital circuits. These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. In a gate, the signal at the
output is logic ‘1’ or ‘0’, following some prescribed logic functions such as the AND, OR, NAND, NOR, XOR,
etc. of the signals at the inputs. The logic function is determined by the internal structure of the gate and the
convention used to define the logic levels (positive or negative logic). In a gate, the output is a function of the
present inputs only.

2. Objectives
The objective of this laboratory is to understand the basic logic gates, their functions and their use in
combinational logic circuits. You will use the knowledge learned during lectures, deploying methods such as
truth table, Karnaugh map (K-map) simplification approach, etc., to characterize and construct customized
combinational logic circuits. The experiments to be conducted are divided into three parts:

Part A — To build arithmetic logic circuits, i.e. a 1-bit half-adder and full-adder logic circuits; and an
arithmetic circuit.
Part B — To use K-map simplification method in designing minimum combinational logic circuits that
drives the seven-segment display.
Part C — To appreciate logic gates through measurements of voltage levels at gate inputs and output,
(Optional) and to characterize other parameters relating to the logic gates.

3. Equipment and Components

DC Power Supply 1 unit
Digital Storage Oscilloscope 1 unit
Function Generator 1 unit
Multimeter 1 unit
Breadboard 1 unit
Switch Box 1 unit
LED Bank 1 unit
*IC type 74LS00 Quad 2-input NAND gate 1
*IC type 74LS04 Hex inverters 1
*IC type 74LS20 Dual 4-input NAND gate 1
*IC type 74LS86 Quad 2-input XOR gate 1
*IC type 74LS83 4-bit adder 1
270 ohm ± 5% resistor 3
Red LED 3
7-Segment Display – Common Cathode 1

*Note: For proper pin configurations, refer to the data sheets of the various TTL IC types provided in the
Appendices. All ICs must be appropriately connected to Vcc and ground.

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4. Logic Families, Logic Gates and Combinational Logic Circuits

4.1 Introduction To Logic Families

Logic gates are classified not just by their logical functions, but also their features and technologies. They are
categorized as logic families. An understanding of the physical capabilities and limitations of a logic element, as
determined by its logic family, are therefore important for proper operation of a digital system. The logic family
refers to the general physical construction of a logical element, such as the transistor-transistor logic (TTL) and
complementary metal-oxide semiconductor (CMOS) logic families. Within each logic family are one or more
logic series that have distinctive characteristics, relative to other series within the same logic family. For
example, in the TTL logic family, there are several logic series: the 74 standard, 74L low-power, 74H high-
speed, 74S standard Schottky, 74LS low-power Schottky series, and 74ALS advanced low-power Schottky
series.

4.2 TTL Family

The TTL family, characterized by its relatively high speed operation, was the most widely used logic family for
several years and has since been replaced mostly by CMOS logic. The physical representation of the binary
logic states in these families are high and low voltages. Assuming positive logic (high voltage for logic 1) in the
74LS TTL family, LOW (L) voltages in the range 0 V to 0.8 V are considered to be logic 0, and HIGH (H) voltages
in the range 2.0 V to 5.25 V are considered to be logic 1. The voltage levels for all possible input combinations
to a two-input NAND gate is shown in Figure 1.

A B Y
A 0 0 1
Y 0 1 1
B
1 0 1
1 1 0

(a) (b)
Figure 1: Logic symbol (a) and its truth table (b) for a two-input NAND gate

You may have wondered why NAND gate is such a popular gate in the TTL logic family. In the TTL family, the
number of transistors required to implement a NAND gate is less than that required to implement other gates
such as AND, OR and NOR. Another important factor that favours the NAND gate is that any combinational
logic functions can be realized using just NAND gates. In this experiment, we will first try to understand some
of the characteristics of the TTL family.

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5. Procedures

Part A – Arithmetic Logic Circuits

A.1 Half-Adder
The half-adder is a simple circuit that adds two single bits, e.g. A(H) and B(H), to yield a sum and a carry output,
S(H) and C(L). Note that C(L) denotes negative logic in which logic 1 is represented by low voltage. The Boolean
expressions for a half-adder are given below:

S(H) = A(H)  B(H) (1)

C(L) = A(H) ∙ B(H) (2)

Use an XOR and a NAND gate to realise the circuit for the half-adder shown in Figure 2. Connect a LED each
to S(H) and C(L). Use a 270Ω resistor in series with each LED and connect them such that the LED will light up
when asserted (the output is logic 1). The LEDs will serve as convenient visual indicator of the output. Hence,
if properly connected, S(H) LED will light up at high voltage and C(L) LED at low voltage. Verify that your circuit
works properly (hint: complete the truth table given in Table 1 and verify). Explain how the LEDs light up for
both S(H) and C(L). Do NOT disconnect the circuit and proceed to Section A.2.

+5V 74LS00
1
3
C(L)
Switch bank 2
A(H) 74LS86
1 3
S(H)
2
B(H)

Figure 2: Half-adder circuit

Table 1: Truth table of half-adder

A(H) B(H) S(H) C(L)

0 0
0 1
1 0
1 1

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A.2 Full-Adder
The full-adder is a common circuit used in many designs of digital electronic circuits, both small and large,
including the processors. A full-adder circuit has three inputs, e.g., A(H), B(H), and Ci(H), and two outputs, So(H)
and Co(H). Build a full-adder using two half-adders based on the circuit configuration shown in Figure 3. Use
LEDs to display the logic levels at Co(H) and So(H). From your circuit, derive the Boolean expressions for S o(H)
and Co(H). Complete Table 2 and derive your Boolean expressions using the truth table and the K-map. Verify
that your expressions are correct.

+5V 74LS00
1
3
2
Switch bank
74LS86
A(H) 1 74LS00
3
2 Co(H)
B(H)

74LS00
Ci(H)

74LS86
So(H)

Figure 3: Full-adder circuit

Table 2: Truth table of full-adder

A(H) B(H) Ci(H) So(H) Co(H)

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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A.3 Arithmetic Circuit

The half-adder and full-adder are basic building blocks for more complex arithmetic circuits such as n-bit adder,
subtractor, multiplier, divider, and circuits for logarithmic and trigonometric functions. The circuit shown in Figure
4 is a 4-bit arithmetic circuit built from four XOR gates and a 4-bit adder 74LS83. The 4-bit adder takes in two
4-bit inputs, A4A3A2A1 and B4B3B2B1, and a carry input c0. It produces a 4-bit sum 4321 and a carry output
c4. Here A4, B4 and 4 are the most significant bits (MSB). The pin layout and the function of the 74LS83 adder
are given in Appendix B. Combining with four XOR gates, a circuit with more complex arithmetic functions is
derived.

x3 x2 x1 x0 y3 y2 y1 y0

A4 A3 A2 A1 B4 B3 B2 B1 c0
74LS83

4-BIT BINARY FULL ADDER

c4 4 3 2 1

cout s3 s2 s1 s0

Figure 4: An arithmetic circuit

Connect up the circuit in Figure 4 with the inputs X = x3x2x1x0, Y = y3y2y1y0 and m to the switch box and the
outputs S = s3s2s1s0 and cout to the LED bank. 6 pairs of X and Y are suggested in Table 3. You should choose
more pairs for the inputs. Test each pair of the inputs and record the corresponding outputs in Table 3. Also
convert the binary numbers to decimal numbers (Hint: apply the knowledge on number systems learnt in Week
1).
Analyze and explain the results in Table 3 and discuss the following questions.
1) What is the function of the input ‘m’?
2) What is the function of the circuit?
3) How is the function of the circuit achieved?

Table 3: Inputs and outputs of Arithmetic Circuit

m X = x3x2x1x0 Y = y3y2y1y0 S = s3s2s1s0 cout
0 0010 ( 2 ) 0100 ( 4 )
1 0010 ( 2 ) 0100 ( 4 )
1 1011 ( ) 0110 ( )
0 1011 ( ) 0110 ( )
0 0000 ( ) 0000 ( )
1 0000 ( ) 0000 ( )

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Part B – Hexadecimal-To-Seven-Segment Display Decoder Circuit

A seven-segment (7-segment) LED display contains seven LEDs. Each LED is called a segment and they are
identified as a, b, c, d, e, f, and g segments. The display has seven inputs, each connected to a LED segment.
There are two types of 7-segment LED display – the common anode type, where all anodes of the LEDs are
tied together and joined to 5 V; and the common cathode type, where all cathodes of the LEDs are tied together
and joined to ground. Using IC such as the MC14495 hexadecimal-to-7 segment latch/decoder LED driver, 4-
bit hexadecimal inputs, e.g. DCBA, where D is the Most Significant Bit (MSB), can be used to drive the 7-
segments, as shown in Figure 5. Note that a decoder is a combinational logic circuit that converts binary
information from n-input lines to a maximum of 2n output lines. Here, the input to the decoder/combination logic
circuit is a hexadecimal number and the outputs of the system are the seven segments a, b, c, d, e, f, and g.

7-segment display
Oa
Ob a
D Decoder /
Combinational Oc f
C Logic Circuit g b
Od
B Oe
e c
A Of
Og d
7 x 220 Ω

Figure 5: Seven segment LED display

In this experiment, you will design a combinational circuit to emulate the decoder function to control only one
segment, i.e., segment “e” of the seven-segment display, as illustrated in Figure 6. You may proceed according
to the following steps below:
1) Using Figure 7, complete the truth table of Table 4; Input DCBA represents the 4-bit hexadecimal
number and Oa to Og are the seven outputs to control each segment of the display. Note that input D is
the MSB.
2) Using the K-map in Figure 8, obtain a minimum sum-of-product logic function for Oe.
3) Using De-Morgan’s theorem, realize your function using 2-input and 4-input NAND gates. Draw your
logic circuit in Figure 9 and connect your circuit with Oe driving a single LED.
4) With the aid of the 4-input switch box, apply hexadecimal inputs and verify that the segment “e” lights
up correctly.

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 Com
g f a b

a
D
Circuit
C to f g b
7-segment display
B Design Oe
e c
A 220 Ω
d h

Com
Note: e d c h
• Input D is the MSB
• You are building only ONE logic circuit (for output Oe), to drive segment “e”
of the 7-segment display

Figure 6: Circuit for control segment “e”.

Figure 7: 7-Segment display segments for hexadecimal numbers.

Table 4: Truth table of a hexadecimal to 7-segment decoder

Hexadecimal Input Output

Number D C B A Oa Ob Oc Od Oe Of Og
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
A 1 0 1 0 1 1 1 0 1 1 1
B 1 0 1 1 0 0 1 1 1 1 1
C 1 1 0 0 1 0 0 1 1 1 0
D 1 1 0 1 0 1 1 1 1 0 1
E 1 1 1 0 1 0 0 1 1 1 1
F 1 1 1 1 1 0 0 0 1 1 1

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 00 01 11 10
00

01

11

10

Figure 8: K-map and Simplified Boolean function

Figure 9: Logic circuit for driving Oe LED segment

Discuss the following questions.

1) What is the purpose of the limiting resistors network, i.e., the 7 x 220  resistors shown in Figure 5?
2) For the simplified function you have obtained, which 7-segment LED display, i.e., common anode or
common cathode type is to be used?
3) How should you modify your circuit to drive the other type of the 7-segment LED display?

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Part C – Voltage Transfer Curve (Optional)

C.1 Threshold Voltage Concept

In a circuit, logic variables (values 0 and 1) can be represented as levels of voltage. The most obvious way of
representing two logic values as voltage levels is to define a threshold voltage; any voltage below the threshold
represents one logic value and voltage above the threshold corresponds to the other logic value.
To understand the threshold-voltage concept, a range of low and high voltage levels is defined – see shaded
regions in Figure 10. As seen in Figure 10, voltages between Gnd to VL,max represent logic ‘0’ whereas those
ranging from VH,min to Vcc corresponds to logic ‘1’. Logic signals do not normally assume voltages in undefined
range except in transition from one logic value to the other.

Voltage

Vcc

Logic ‘1’
VH,min

Undefine

V L,max

Logic ‘0’
Gnd
Figure 10: Representation of logic values through voltage levels

C.2 Voltage Transfer Curve

A voltage transfer curve (VTC) is a graph of the input voltage to a gate versus its output voltage. Using the setup
shown in Figure 11, we can obtain the VTC of a TTL NOT gate, i.e., 74LS04.

Oscilloscope

Function Generator
2.5-Vp-p
Sawt oot h Wave, CH 1 CH 2
at 1 kHz
74LS04
Vin Vout

Figure 11: Setup for deriving VTC of a NOT gate.

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Follow the steps below to obtain the VTC.
1) Before connecting your circuit, set the function generator to provide a 1 kHz triangular wave and
observe the waveform using Channel 1 of the oscilloscope. To turn on Channel 1 of the oscilloscope,
press the CH 1 button.
2) To simulate a sawtooth waveform, press “Ramp”. Select Ramp Parameter Menu and Set to 100%.
Press Amplitude, set to 2.5Vp-p and offset to 1.25V. Warning: The input waveform should never
exceed 5 Vpeak at any time; else the gate may be damage.
3) Now, connect the circuit of Figure 11, with the gate input, Vin to Channel 1 and gate output, Vout to
Channel 2. You may use any of the six inverters in the 74LS04 IC. Turn on Channel 2 by pressing CH
2 button and you should see a square wave display on the screen.
4) In order to plot Channel 1 vs. Channel 2, press the DISPLAY menu button located at the top right of the
front panel. This will bring up another menu along the right side of the screen. Press to change Format
YT to XY. The resulting plot of Vout vs. Vin is the VTC of the NOT gate.
5) Choose appropriate volts/div. scales to maximize the waveform on the screen. You can do so by
temporarily setting the input couplings on Channels 1 and 2 to ground to display a dot on the screen.
The dot signifies zero vertical and horizontal voltage potential. Move the dot to the bottom left corner of
the screen. You may now set the coupling back to DC and adjust to appropriate scales for the best
display of the VTC and draw your curve on the grids provided.
6) The gate threshold voltage is the voltage on the transfer curve at which Vout = Vin. Determine this voltage
from the VTC.
7) The noise margins of a logic gate are defined as follows:
High Noise Margin = VOH(min) – VIH(min), and
Low Noise Margin = VIL(max) – VOL(max).
Estimate both VIL and VIH from the curve. Assume VOL = 0.4 V, and VOH = 2.4 V (or you may use the
actual values provided in the datasheet), work out the high and low noise margins for the NOT gate.

Graph 1: Voltage transfer curve

Discuss the following questions.

1) Instead of a sawtooth wave, can a triangular wave be used as the input? Explain your answer.
2) Test out the circuit with a sine wave input and comment on your result.
3) How about testing the circuit with a square wave input? Can you obtain the VTC and why?

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6. References

[1] Wakerly John F, Digital Design: Principles and Practices, 4th Edition, Pearson Prentice-Hall, 2007.
[2] Roth Charles H and Kinney Larry L, Fundamentals of Logic Design, 7th Edition, Cengage Learning,
2014.
[3] Mano M Morris and Ciletti Michael D, Digital Design: With an Introduction to the Verilog HDL, 5th Edition,
Pearson Prentice Hall, 2013.

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APPENDIX A – LABORATORY REGULATIONS AND SAFETY RULES

The following Safety Rules and Regulations must be observed at all time when in the laboratory.
1. It is the duty of all laboratory users to take all sensible steps to safeguard the HEALTH and SAFETY of
themselves and all other users and visitors.
2. Laboratory users are to be in proper attire and wear covered shoes when conducting the laboratory
exercises.
3. Students are only allowed to use the equipment indicated/provided in the experiment manual. Students
are not allowed to use any equipment without proper orientation and hands on equipment training. If in
doubt, ask for assistance.
4. Ensure all equipment is functioning properly before using them. Any defective equipment must be
reported immediately to the laboratory instructor or technical support staff.
5. Read the laboratory manual in advance before attending the laboratory session. Understand what you
are supposed to do and plan your experiments.
6. Never turn on the power supply until you are sure of your circuit connection and confident that it is safe
to switch on the power.
7. For good practice, ensure that the last connection to be made in your circuit is the power supply and
first to be disconnected is also the power supply. The careless use of electricity can lead to two
consequences: it can hurt you and/or your laboratory partner and you may damage the laboratory
equipment.
8. Do not leave wires dangling about/around your bench.
9. Do not hold electrified wire, and make sure that no part of your body inadvertently comes into contact
with a wire.
10. When probing a circuit with a test lead, be absolutely sure that you are making contact with the exact
points you wish to test, and ONLY those points.
11. To protect equipment, make sure that all the hookups between power supplies, oscilloscopes, volt-ohm
meters, light emitting diodes (LED's), breadboard, Integrated Circuits (ICs), etc., are as you want them
to be. Double check all wiring prior to turning on the power. If you accidentally reverse the power leads,
you may damage an IC or a passive component. An abused IC will start smoking or will get so hot that
you cannot touch it and has to throw it away.
12. When using a particular piece of test equipment, understand the limitations of the equipment. Do not
attempt to use it to for other tests it is not designed for.
13. Special attentions are to be paid to “hot” items at the work bench or sharp tools.
14. Equipment should not be removed, transferred to other location without permission from the laboratory
technical support staff.
15. Disconnect the power supplies from the circuit and switch off all equipment before leaving the
laboratory.
16. Observe cleanliness and proper laboratory housekeeping of the equipment and other related
accessories.
17. Smoking and drinking in the laboratory are not permitted.

All the above rules and regulations are necessary precaution in the EEE Laboratory to safeguard the students,
laboratory technical support staff, the equipment and all other laboratory users. The best way to prevent yourself
and the equipment from being damaged is to do everything slowly and vigilantly.

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APPENDIX B – DATASHEETS

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