10.

∗
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner

Jackey Z. Yan Chris Chu

Department of Electrical and Computer Engineering
Iowa State University, Ames, IA 50010
{zijunyan, cnchu}@iastate.edu

ABSTRACT
termines the top-level spatial structure of a chip, but also initially op-
In this paper, we present DeFer — a fast, high-quality and non-
timizes the interconnections. Thus a good floorplan solution among
stochastic fixed-outline floorplanning algorithm. DeFer generates a
circuit modules definitely has a positive impact on the placement,
non-slicing floorplan by compacting a slicing floorplan. To find a
routing and even manufacturing. In the nanometer scale era, the ever-
good slicing floorplan, instead of searching through numerous slic-
increasing complexity of ICs promotes the prevalence of hierarchical
ing trees by simulated annealing as in traditional approaches, DeFer
design. However, as pointed out by Kahng [1], classical outline-free
considers only one single slicing tree. However, we generalize the
floorplanning [2] can not satisfy such requirements of modern de-
notion of slicing tree based on the principle of Deferred Decision
signs. In contrast, fixed-outline floorplanning enabling the hierarchi-
Making (DDM). When two subfloorplans are combined at each node
cal framework is preferred by modern ASIC designs. Nevertheless,
of the generalized slicing tree, DeFer does not specify their orienta-
fixed-outline floorplanning has been shown to be much more diffi-
tions, the left-right/top-bottom order between them, and the slice line
cult, compared with classical outline-free floorplanning, even with-
direction. DeFer even does not specify the slicing tree structures for
out considering the wirelength optimization [3].
small subfloorplans. In other words, we are deferring the decisions
on these factors, which are specified arbitrarily at an early step in
traditional approaches. Because of DDM, one slicing tree actually
1.1 Previous Work
Simulated annealing has been the most popular method of explor-
corresponds to a huge number of slicing floorplan solutions, all of
ing good solutions on the fixed-outline floorplanning problem. Using
which are efficiently kept in one single shape curve. With the final
sequence pairs representation, Adya et al. [4] modified the objective
shape curve, it is straightforward to choose a good floorplan fitting
function, and proposed a few new moves based on slacks computa-
into the fixed outline. Several techniques are also proposed to further
tion to guide a better local search. In [5], Chen et al. adopted the
optimize the wirelength. Experimental results on benchmarks with
B*-tree [6] structure representing the geometric relationships among
only hard blocks and with both hard and soft blocks show that DeFer
modules, and performed a novel 3-stage cooling schedule to speed
achieves the best success rate, the best wirelength and the best run-
up the annealing process. To improve the floorplanning scalabil-
time on average compared with other state-of-the-art floorplanners.
ity, in [7] a multilevel partitioning step was performed beforehand
on the original circuit. Different from traditional multilevel frame-
Categories and Subject Descriptors works, a top-down uncoarsing followed by a bottom-up coarsening
B.7.2 [Hardware, Integrated Circuits, Design Aids]: Layout approach were adopted. Most recently, by enumerating the positions
in sequence pairs during the searching process, Chen et al. [8] ap-
General Terms plied Insertion after Remove (IAR) to accelerate the original local
searching. As a result, both the runtime and success rate1 have been
Algorithms, Design, Performance
enhanced dramatically. All of the above techniques are based on sim-
Keywords ulated annealing. Generally the authors tried various approaches to
improve the algorithm efficiency. However, one common drawback
Fixed Outline, Floorplanning, Deferred Decision Making is that these techniques become quite slow when the size of circuits
grows large, e.g., 100 modules. Additionally the annealing-based
1. INTRODUCTION techniques always have a hard time handling circuits with soft mod-
Floorplanning has become a very crucial step in modern VLSI de- ules, because they need to search an extremely large solution space,
signs. As the start of physical design flow, floorplanning not only de- which takes a long time to finish.
Some researchers have adopted non-stochastic methods. Sassone
∗This work was supported by NSF under grant CCF-0540998. et al. [9] proposed a row-oriented block packing technique which
organizes the modules by rows based on their dimensions. How-
ever, the technique cannot handle soft modules. In [10], Zhan et
al. applied a quadratic analytical approach similar to those used for
Permission to make digital or hard copies of all or part of this work for placement problems. To generate a non-overlapping floorplan, the
personal or classroom use is granted without fee provided that copies are quadratic approach relies on a legalization process. However, this
not made or distributed for profit or commercial advantage and that copies legalization is very difficult for circuits with big hard macros. Cong
bear this notice and the full citation on the first page. To copy otherwise, to et al. [11] presented an area-driven look-ahead floorplanner in a hi-
republish, to post on servers or to redistribute to lists, requires prior specific
permission and/or a fee. 1
DAC 2008, June 8–13, 2008, Anaheim, California, USA. The success rate is defined as the ratio of the number of runs resulting a layout within
Copyright 2008 ACM ACM 978-1-60558-115-6/08/0006 ...$5.00. fixed-die, to the total number of runs.

161
erarchical framework. Two main techniques were used in their algo- H H Final shape curve
Fixed outline
rithm: the row-oriented block packing (ROB) and zero-dead space
Valid solutions No Valid solutions
(ZDS). To handle both hard and soft modules, ROB was extended
from [9]. ZDS was used to pack soft modules. Nevertheless, ROB
may generate a layout with large whitespace when the module sizes
within a subfloorplan are quite different from each other, e.g., a de-
sign with big hard macros. (0, 0) W (0, 0) W
(a) m > 0 (b) m = 0
1.2 Our Contributions Figure 1: Final shape curve with fixed outline and candidate points.
This paper presents a fast, high-quality, and non-stochastic fixed-
outline floorplanner called DeFer. It can handle both hard and soft Mirroring. The motivation is to greedily optimize the wire-
modules. Experimental results show that, compared with other state- length among the modules.
of-the-art floorplanners, DeFer achieves the best success rate, the
best wirelength and the best runtime on average for benchmarks with The rest of this paper is organized as follows. Section 2 describes
only hard blocks and with both hard and soft blocks. the overview of the algorithm. Section 3 introduces the generalized
DeFer generates a final non-slicing floorplan by compacting a slic- slicing tree. Section 4 describes the Enumerative Packing technique.
ing floorplan. It has been proved in [12] that any compact non- Section 5 illustrates the Block Swapping and Mirroring. Experimen-
slicing floorplan can be generated by the compaction. In traditional tal results are presented in Section 6. Finally, this paper ends with a
annealing-based approaches, obtaining a good slicing floorplan usu- conclusion and the direction of future work.
ally takes a long time. Because the algorithms have to search as
many slicing trees as possible, such that the “local minimum” can 2. OVERVIEW OF THE ALGORITHM
be possibly avoided. By comparison, DeFer considers only one sin-
gle slicing tree. However, to guarantee that a large solution space is Essentially, DeFer has five steps. By initially deferring the deci-
explored, we generalize the notion of slicing tree based on the prin- sions in Steps 1 and 2, DeFer explores a huge collection of slicing
ciple of Deferred Decision Making (DDM). When two subfloorplans layouts, all of which are efficiently kept in one final shape curve at the
are combined at each node of the generalized slicing tree, DeFer does top; By finally making the decisions in Steps 3 and 4, DeFer chooses
not specify their orientations, the left-right/top-bottom order between good slicing layouts fitting into the fixed outline. The algorithm flow
them, and the slice line direction. For small subfloorplans, DeFer is as follows.
even does not specify the slicing tree structures. In other words, we 1. Partitioning Step: As the number of modules in one design
are deferring the decisions on these four factors correspondingly: (1) becomes large, exploring all slicing layout solutions among
Subfloorplan Orientation; (2) Subfloorplan Order; (3) Slice Line Di- them is very expensive. Thus, the purpose of this step is to di-
rection; (4) Slicing Tree Structure. Note that traditional annealing- vide one original circuit into several small subcircuits, and ini-
based approaches specify these factors arbitrarily at an early step. tially minimize the interconnections among them. hMetis [13],
Because of DDM, one slicing tree actually represents a huge num- the state-of-the-art hypergraph partitioner, is called to perform
ber of slicing floorplan solutions. Moreover, all of these solutions a recursive bi-sectioning on the circuit, until every subcircuit
are efficiently kept by only one single shape curve. With the final contains less than or equal to maxN modules (maxN = 10 by
shape curve, it is straightforward to choose a good slicing floorplan default). During this process, a high-level slicing tree structure
fitting into the fixed outline. To realize the DDM idea, we propose is built up where each leaf node represents a subcircuit. Due
the following techniques: to the generalized notion of slicing tree, the whole slicing tree
not only sets up a hierarchical framework, but also represents
• Generalized Slicing Tree — To defer the decisions on these many possible packing solutions among the subcircuits.
three factors: (1) Subfloorplan Orientation; (2) Subfloorplan
Order; (3) Slice Line Direction, we generalize the original slic- 2. Combining Step: In this step, we first defer the decision on
ing tree [2]. In the generalized slicing tree, one tree node can the slicing tree structure of each subcircuit, by applying the
represent both orientations of its two child nodes, both orders Enumerative Packing technique to explore all slicing packing
between them and both horizontal and vertical slice lines. In layouts within the subcircuit. After that, an associated shape
order to carry out the according combination of such new slic- curve representing these possible layouts for each subcircuit
ing trees, original shape curve [2] operations are extended to is produced. Then, based on the hierarchical framework in
curve flipping and curve merging. In this paper all slicing trees Step 1, DeFer traverses from bottom-up constructing a shape
and shape curve operations mean the generalized version by curve for every tree node. The final shape curve at the top will
default. hold all explored slicing floorplan layouts of the whole circuit.

• Enumerative Packing — To defer the decision on the slicing 3. Back-tracing Step: Once the final shape curve is available,
tree structure among a set of modules, we develop the Enumer- it is fairly straightforward to choose the points fitting into the
ative Packing (EP) technique. It can enumerate all possible fixed outline (see Fig. 1). However, we have three cases here.
slicing tree structures and build up one shape curve capturing Let m be the number of points enclosed into the fixed outline,
all slicing layouts among the modules. This computation could and to make a trade-off between runtime and solution qual-
be extremely expensive in terms of CPU time and memory us- ity, DeFer chooses K points at most (K = 11 by default).
age. But using the technique of dynamic programming, EP (1) If m > K, based on the geometric observation between
can be efficiently applied to up to 10 modules. aspect ratio and wirelength in [8], only K points are chosen
such that the aspect ratio is nearest to 1; (2) If 0 < m ≤ K,
• Block Swapping and Mirroring — To make the decision on all m points are chosen; (3) If m = 0, DeFer still chooses
the subfloorplan order (left-right or top-bottom), we propose at most K points near the upper-right corner of the fixed out-
three techniques: Rough Swapping, Detailed Swapping, and line (see Fig. 1 (b)), in that we will try to compact them into

162
 the fixed outline in Step 5. For each of the points we choose, a B B

A
A A

B
B
back-tracing process is applied. Since every point in the parent B A B

A
A

B
curve is generated by adding two points from two child curves, B

A B
B

B
the back-tracing can be propagated from the top to the bottom

A
A A

level. During this process, the decisions on every subfloor- A B

A
A

B A
A
plan orientation, slice line direction and slicing tree structure B B

B
of each subcircuit are also made.
Figure 2: Generalized slicing tree and sixteen different layouts.
4. Swapping Step: The fourth step is to make decisions on the H H H
Cv
A B Cv
subfloorplan order. As pointed out in [11], in slicing struc- Ch
tures switching the left-right or top-bottom order of two child W = H W=H k k’ W = H
subfloorplans would not change the dimension of their par-
ent floorplan outline, but it may actually improve the intercon-
nections. Different from the previous work, we execute three Ch C Ch
rounds of various wirelength refinement processes through the
W W W
hierarchical framework. In the first round, we apply Rough (a) Addition (b) Flipping (c) Merging
Swapping technique from top-down, followed by a second round
with Detailed Swapping. Finally, Mirroring is applied to fur- Figure 3: Extended shape curve operations.
ther improve the wirelength and fix the order between every
pair of child subfloorplans. develop three steps to combine two child curves A and B into one
parent curve C (see Fig. 3).
5. Compacting Step: After fixing the slicing floorplan structure,
the last step is that of compacting all modules to the center of 1. Addition: Firstly, we add two curves A and B horizontally to
the fixed outline. The compaction can put modules nearer to get curve Ch , on which each point corresponds to a horizontal
each other, such that the wirelength is further reduced. The combination of two subfloorplan layouts from A and B.
candidate floorplan with the best wirelength is the final out-
put solution. If previous floorplan is outside of the fixed out- 2. Flipping: Next, we flip curve Ch symmetrically based on the
line, instead of compacting modules to the center, DeFer com- W = H line to derive curve Cv . The purpose of doing this is
pacts them to the lower-left corner, so that potentially there is to generate the curve that contains the corresponding vertical
a higher chance to find a valid layout within the fixed outline. combination cases from the two subfloorplan layouts.
If it still fails, then DeFer would restart from Step 1, and try 3. Merging: The final step is to merge Ch and Cv into the parent
another run. By default DeFer attempts 5 runs at most. curve C. In the merging, for a given height, the point with a
The main techniques are discussed in detail in Sections 3-5. smaller width out of Ch and Cv will be taken (see Fig. 3 (c)).

As a result, we have derived three shape curve operations which

3. GENERALIZED SLICING TREE correspond to the ‘⊕’ operation in the associated slicing tree combi-
In this section, we introduce the generalized slicing tree, which nation. Now given two child shape curves corresponding to two child
enables the deferred decisions on the first three factors. subfloorplans in the slicing tree, the new operations can be applied to
In an ordinary slicing tree, the parent tree node of two child sub- combine these two curves into one parent curve, in which the entire
floorplans A and B can be labeled ‘H’ (‘V’) to specify that A and slicing layouts between the two subfloorplans are captured.
B are separated by a horizontal (vertical) slice line. In addition, the Sometimes it is not necessary to hold a huge number of points
order between the two child nodes in the slicing tree specifies the on the curve, especially at the later stage. Considering the trade-off
top-bottom (left-right) order of A and B in the layout. For exam- between runtime and solution quality, in the current implementation
ple, if A is on the left of B, then in the ordinary slicing tree, the left DeFer keeps at most 1000 points for each shape curve. This pruning
child is A, the right child is B, and the parent node is labeled ‘V’. strategy makes our algorithm even faster. In spite of this, however,
However, if we want to switch to other layouts between A and B, DeFer still reaches the highest success rate among all floorplanners.
then the previous slicing tree has to be changed as well. Considering
the huge amount of layout possibilities, the constraint of the ordinary 4. ENUMERATIVE PACKING
representation becomes obvious.
In order to defer the decision on the slicing tree structure, we pro-
Here we introduce a new operator — ‘⊕’ to incorporate both ‘H’
pose the Enumerative Packing (EP) technique that can efficiently
and ‘V’ slice line directions. Additionally we do not differentiate the
enumerate all possible slicing structures among a set of modules,
‘top-bottom’ or ‘left-right’ order between the two child subfloorplans
and finally keep all slicing layouts into one shape curve.
any more, which means even though we put A at the left child, it can
be switched to the right later on. In [14], only the orientation for 4.1 A Naive Approach of Enumeration
each module has been generalized. Here, we even do not specify the In this subsection, we plot out a naive way to enumerate all slicing
orientation for each subfloorplan. As a result, the decisions on Sub- packing solutions among n modules. We first enumerate all slicing
floorplan Orientation, Subfloorplan Order and Slice Line Direction tree structures and then enumerate all permutations of the modules.
are deferred. Now each parent node in the slicing tree represents all The complete slicing tree structures for 3 to 6 modules are listed in
sixteen slicing layouts between two child subfloorplans (see Fig. 2). Figure 4. Note that we are using the generalized slicing tree which
Since the slicing tree is only a structural representation of different does not differentiate the left-right order between two child subtrees.
layouts between two subfloorplans, to actualize the combination we From Figure 4, we notice that the number of different slicing tree
use the corresponding shape curve operations, and each subfloorplan structures is actually very limited.
layout property is captured by its associated shape curve. In order To completely explore all slicing packing solutions among n mod-
to derive such compatible operations for the new operator —‘⊕’, we ules, for each slicing tree structure, different permutations of the

163
 n # of ⊕ # of ⊕
T3 T4a T4b T5a T5b T5c by naive approach with DP
4 5 5 2 1 1
3
1 2 3 1 2 3 4 4 3 4 5 3 6 6
3 1 2 3 41 2 4 45 25
1 2
5 400 90
1 2
6 4,155 301
T6a T6b T6c T6d T6e T 6f 7 49,686 966
6 6 6 8 674,877 3,025
5 5 4 5 6 5 6 3 6 9 10,295,316 9,330
4 2 4 5
10 174,729,015 28,501
4 3 4 5 3 1 2 3 1

3
Table 1: Comparison on # of ‘⊕’ operation.
1 2 3 41 2 1 2
1 2
A C Big
Figure 4: List of different slicing tree structures. Q Big Macro
Macro B D
T4b T4a
modules should also be considered. For example in Figure 4, in High-Level
tree T4a four modules A, B, C and D can be mapped to leaves EP Big
“1−2−3−4” by the order “A−B −C −D” or “A−C −B −D”. Macro
Big T4b T4a
Obviously these two orders derive two different layouts. However, Macro
A
again because the generalized slicing tree does not differentiate the B
A C
left-right order between two child subtrees which share the same par- D B C D
ent node, for example, orders “A−B−C−D” and “B−A−C−D” (a) (b) (c)
are exactly the same in T4a . After pruning such redundancy, we have
4! Figure 5: Illustration of high-level EP.
2
= 12 non-redundant permutations for mapping four modules to
the four leaves in T4a . Therefore, for each slicing tree structure of
n modules, we first enumerate all non-redundant permutations, for However, if the set contains too many modules, two problems ap-
each one of which a shape curve is produced, and then merge these pear in EP: 1) The memory to store results from previous sets can be
curves into one curve associated with each slicing tree structure. Fi- expensive; 2) Since the interconnections among the modules are not
nally, these curves from all slicing tree structures are merged into considered, the wirelength may be increased. Due to these two con-
one curve that captures all possible slicing layouts among these n cerns, in the first step of DeFer, we apply hMetis to recursively cut
modules. To show the amount of computations in this process, we the original circuit into a bunch of smaller subcircuits. This process
list the number of ‘⊕’ operations for different numbers of modules not only helps us to cut down the number of modules in each subcir-
in the second column of Table 1. cuit, but initially optimizes the wirelength as well. Later on as ap-
plying EP within each subcircuit, the wirelength would not become a
4.2 Enumeration by Dynamic Programming big concern, because this is only a locally packing exploration among
Table 1 shows that the naive approach can be extremely expensive a small number of modules. In other words, in the spirit of DDM, in-
in both runtime and memory usage. Alternatively, we notice that the stead of deferring the decision on the slicing tree structure among all
shape curve for a set of modules (M ) can be defined recursively by modules in the circuit, first we fix the high-level slicing tree structure
Equation 1 below. among the subcircuits by partitioning, and then defer the decision on
the slicing tree structure among the modules within each subcircuit.
S(M ) = MERGE (S(A) ⊕ S(B)) (1) 4.4 Extension of EP at High-Level
A⊂M,B=M −A
In the modern SoCs design, the usage of Intellectual Property (IP)
S(M ) is a shape curve capturing all slicing layouts among mod- becomes more and more popular, which makes a circuit usually con-
ules in M , MERGE() is similar to the Merging in Figure 3 (c), but tain numbers of big hard macros. Due to the large size differences
operates on shape curves from different sets. Based on Equation 1, from other small or medium modules, they may produce some large
we can use Dynamical Programming (DP) to implement the shape deadspaces. For example in Figure 5 (a), after the partitioning step,
curve generation. First of all, we generate the shape curve represent- an original circuit has been cut into four subcircuits A, B, C and
ing the outline(s) of each module. For hard modules, there are two D. Subcircuit A contains a big hard macro. Respecting the slicing
points2 in each curve. For soft modules, only several points from tree structure of T4b , you may find that no matter how hard EP ex-
each original curve are sampled. And then starting from the smallest plores various packing layouts within subcircuits A or B, there is
subset of modules, we proceed to build up the shape curves for the always a large deadspace, such as Q, in the parent subfloorplan. This
larger subsets step by step, until the shape curve S(M ) is generated. is because the high-level slicing tree structure among subcircuits has
Since in this process the previously generated curves can be reused been fixed by partitioning, so that some small subcircuit is forced to
for building up the curves of larger subsets of modules, many redun- combine with some large subcircuit. Thus, to solve this problem, we
dant computations are eliminated. After applying DP, the resulted need to explore other slicing tree structures among the subcircuits.
numbers of ‘⊕’ operations are listed in the third column of Table 1. To do so, in addition to applying EP on a set of modules, we use
4.3 Impact of EP on Packing it on a set of subfloorplans. In Figure 5 (b), EP is applied on the
To control the quality of packing in EP, we can adjust the number four shape curves coming from subfloorplans A, B, C and D, re-
of modules in the set. Consequently the impact on packing is: the spectively. Hence, all slicing tree structures (T4a and T4b ) and per-
more modules a set contains, the more different slicing tree structures mutations among these subfloorplans can be completely explored.
we explore, the more slicing layout possibilities we have, and thus the Eventually one tightly-packed slicing layout can be chosen during
better quality of packing we will gain at the top level. the back-tracing step (see Fig. 5 (c)). For the current implementation,
in the high-level slicing tree if the total area of big hard macros in
2
One point if the hard module is a square. one subfloorplan is more than 55% of this subfloorplan area, DeFer

164
 Swapping Mirroring axis wirelength is calculated using HPWL. For each circuit, we choose 3
different fixed-outline aspect ratios: 1, 2 and 3 with the same maxi-
mum percentage of white space γ = 10%. Every floorplanner runs
100 times for each test case, and the results are averaged over all
C E successful runs. Note that because PATOMA has fixed the seed of
C E E C
hMetis internally, and produces the same result no matter how many
Figure 6: Swapping and mirroring. times it runs for the same test case, we run it only once. For IMF and
net o neto DeFer, this seed is the same as the index of each run. For each type
of benchmark, we finally normalize all results to DeFer’s results.
net i net i
net o net o The first set of experiment performs on GSRC Hard-Block Bench-
A net o A marks [15] with 100, 200 and 300 hard modules. DeFer compares
B B neto
netcd D D with four floorplanners: Parquet 4.5 [4], IMF [7], IARFP [8] and
C C netcd
PATOMA [11]. All I/O pads are scaled to the boundary. Parquet 4.5
runs in wirelength minimization mode, and the parameters for other
(a) (b) floorplanners are defaulted. The results are summarized in Table 2.
Figure 7: Illustration of motivation on Rough Swapping. For every test case DeFer reaches a 100% success rate. At the same
time, DeFer generates 39%, 16% and 17% better wirelength in 99×,
would apply EP to further explore the various slicing tree structures 87× and 16× faster runtime than Parquet 4.5, IMF and IARFP, re-
of that subfloorplan. spectively. From the authors of [8], we also get a second version of
IARFP in which the parameters are tuned specifically to individual
circuits. For this version, the average success rate is close to 100%,
5. BLOCK SWAPPING AND MIRRORING but the total runtime and wirelength are typically worse than the first
After the back-tracing step, the decision on subfloorplan order version. Compared with PATOMA, DeFer is 1.8× slower. However,
(left-right or top-bottom) has not been made yet. Making use of this considering the total runtime is so short and DeFer achieves 2.25×
property, this section focuses on optimizing the wirelength. higher success rate with even 45% better wirelength, this slowdown
Basically, we develop three techniques here: (1) Rough Swap- is acceptable.
ping; (2) Detailed Swapping; (3) Mirroring. Each of them is trying Second, we compare DeFer with PATOMA on the HB Benchmarks
to switch the positions of two subfloorplans to improve the Half- [16]. These circuits are generated from the IBM/ISPD98 suite con-
Perimeter Wirelength (HPWL). Figure 6 illustrates the differences taining both hard and soft modules ranging from 500 to 2000, some
between Swapping and Mirroring. In Mirroring, instead of simply of which are big hard macros. Detailed statistics are listed in the sec-
swapping two subfloorplans, we first figure out the symmetrical axis ond column of Table 3. The positions of I/O pads are the same as
of the outline at their parent floorplan, and then attempt to mirror what the benchmark specifies. From Table 3, we can see that DeFer
them based on this axis. When calculating the HPWL, in Rough does not achieve 100% success rate for only three test cases, and the
Swapping we treat all internal modules to be at the center of their success rate is 2.22× higher than PATOMA. In terms of the wire-
subfloorplan outline. In contrast, in Detailed Swapping we use the length, DeFer is also 26% better on average, while 3.85× faster than
actual center coordinates of each module in calculating the HPWL. PATOMA. We also run Parquet 4.5 on this benchmark. However, it
Now we want to address the importance of Rough Swapping. For is so slow that even running one test case once takes thousands of
example in Figure 7, when we try to swap two subfloorplans A and seconds. So for each test case, we only run it once instead of 100
B, two types of nets need to be considered: internal nets neti be- times, but none of the results fit into the fixed outline. This suite of
tween A and B, and external nets neto between the modules inside benchmarks is considered to be extremely hard to handle, because
A or B and other outside modules or fixed pads. Let C and D be two it not only contains both hard and soft modules, but also big hard
modules inside A and B, respectively. Modules C and D are highly macros. As far as we know, only the above three floorplanners can
connected by netcd . After the back-tracing step, the coordinates of handle soft modules. Obviously, DeFer reaches the best results.
C and D are still unknown. If we randomly specify the positions
of C and D as shown in Figure 7 (a), then we may swap A and B
to gain better wirelength. Alternatively, if C and D are specified in 7. CONCLUSION
the positions in Figure 7 (b), then we may not swap them. As we As the earliest stage of VLSI physical design, floorplanning has
can see, the randomly specified module position may mislead us to numerous impacts on the final performance of ICs. In this work, we
make the wrong decision. To avoid such “noise” generated by neti have proposed a fast, high-quality and non-stochastic fixed-outline
in the swapping process, the best thing to do is to assume C, D and floorplanner DeFer. Based on the principle of Deferred Decision
all modules inside subfloorplans A and B are at the centers of A and Making, DeFer over-performs all other state-of-the-art floorplanners
B, such that the right decision can be made based on neto . in every aspect. Such a high-quality and efficient floorplanner is ex-
Essentially, we first apply Rough Swapping to the floorplan from pected to handle the increasing complexity of modern ASIC designs.
top-down, followed by a second round with Detailed Swapping. Fi- In the future, we will further improve the algorithm quality by refin-
nally, Mirroring is applied to further optimize the wirelength. ing the pruning and high-level EP strategies. We are also considering
integrating DeFer into placement tools to handle large-scale mixed-
6. EXPERIMENTAL RESULTS size designs.
In this section, we present the experimental results. We com-
pare DeFer with all the best publicly available state-of-the-art fixed- Acknowledgments
outline floorplanners. All experiments were performed on a Linux
machine with Intel Core Duo3 1.86 GHz CPU and 2GB memory. The The authors would like to thank the UCLA CAD group, Song Chen,
and Tung-Chieh Chen for the help with PATOMA, IARFP and IMF,
3
In the experiments, only one core was used. respectively.

165
 Circuit Aspect Parquet 4.5 [4] IMF [7] IARFP [8] PATOMA [11] DeFer
Ratio Suc% HPWL Time(s) Suc% HPWL Time(s) Suc% HPWL Time(s) Suc% HPWL Time(s) Suc% HPWL Time(s)
1 36% 251552 10.10 100% 250680 7.62 100% 219644 3.98 0% — — 100% 208134 0.26
n100 2 37% 300782 10.45 100% 275867 9.83 97% 273423 4.24 0% — — 100% 228001 0.26
3 23% 352371 11.09 100% 303861 11.23 91% 339150 4.50 0% — — 100% 249813 0.26
1 30% 469482 42.40 100% 438467 41.17 97% 393508 6.86 0% — — 100% 377126 0.42
n200 2 19% 556552 42.01 98% 457053 43.96 71% 464706 7.26 100% 550060 0.22 100% 405436 0.39
3 12% 647905 49.91 99% 489045 46.87 28% 562239 7.52 0% — — 100% 435186 0.40
1 25% 683770 96.08 100% 584578 74.34 71% 549530 8.49 100% 653711 0.35 100% 501348 0.62
n300 2 14% 797195 91.04 100% 604471 68.35 10% 636372 8.96 100% 796725 0.32 100% 537460 0.61
3 13% 942869 79.69 100% 638384 70.15 0% — — 100% 949580 0.34 100% 578879 0.60
Norm 0.232 1.39 98.99 0.997 1.16 87.35 0.628 1.17 16.40 0.444 1.45 0.55 1 1 1
Table 2: Comparison with other floorplanners on GSRC Hard-Block Benchmarks.

8. REFERENCES
[1] A. B. Kahng. Classical Floorplanning Harmful? In Proc.
ISPD, pp. 207–213, 2000.
Cir #S./#H. A.R. PATOMA DeFer
ibm /#N. Suc% WL(e6 ) Time(s) Suc% WL(e6 ) Time(s)
[2] R. H. J. M. Otten. Efficient Floorplan Optimization. In Proc.
665 1 100% 2.60 8.52 100% 2.69 1.52
ICCD, pp. 499–502, 1983.
01 /246 2 0% — — 100% 2.78 1.53 [3] S. N. Adya and I. L. Markov. Fixed-outline Floorplanning
/4236 3 100% 5.60 1.79 100% 2.85 1.51 Through Better Local Search. In Proc. ICCD, pp. 328–334,
1200 1 0% — — 100% 6.22 5.25
02 /271 2 0% — — 97% 6.59 7.17
2001.
/7652 3 0% — — 100% 6.39 4.73 [4] S. N. Adya and I. L. Markov. Fixed-outline Floorplanning:
999 1 100% 12.83 5.83 100% 8.86 3.40 Enabling Hierarchical Design. In IEEE Transactions on VLSI
03 /290 2 100% 12.77 4.88 100% 8.68 3.43
/7956 3 0% — — 100% 8.88 3.43
Systems, vol. 11, no. 6, pp. 1120–1135, 2003.
1289 1 0% — — 100% 9.22 4.14 [5] T.- C. Chen and Y.- W. Chang. Modern Floorplanning Based
04 /295 2 0% — — 86% 9.41 8.45 on Fast Simulated Annealing. In Proc. ISPD, pp. 104–112,
/10055 3 0% — — 100% 9.49 3.90
2005.
564 1 100% 12.49 14.00 100% 12.82 2.93
05 /0 2 100% 12.97 13.45 100% 12.94 2.93 [6] Y. C. Wang, Y. W. Chang, G. M. Wu and S. W. Wu. B*-Tree:
/7887 3 100% 13.48 13.17 100% 13.62 2.93 A New Representation for Non-Slicing Floorplans. In Proc.
571 1 0% — — 100% 7.80 3.07 DAC, pp. 458–463, 2000.
06 /178 2 0% — — 100% 7.69 2.96
/7211 3 0% — — 100% 7.89 3.07 [7] T.- C. Chen, Y.- W. Chang and S.- C. Lin. IMF:
829 1 0% — — 100% 14.37 5.38 Interconnect-Driven Multilevel Floorplanning for Large-Scale
07 /291 2 100% 25.09 7.77 100% 14.51 4.92 Building-Module Designs. In Proc. ICCAD, pp. 159–164,
/11109 3 100% 24.68 7.33 100% 14.94 4.64
968 1 0% — — 100% 14.24 6.39 2005.
08 /301 2 0% — — 100% 14.22 6.27 [8] S. Chen and T. Yosihmura. A Stable Fixed-Outline
/11536 3 0% — — 100% 14.44 6.39 Floorplanning Method. In Proc. ISPD, pp. 119–126, 2007.
860 1 0% — — 100% 13.14 4.72
09 /253 2 0% — — 100% 13.12 4.73 [9] P. G. Sassone and S. K. Lim. A Novel Geometric Algorithm
/11008 3 100% 12.58 19.6 100% 13.33 4.74 for Fast Wire-Optimized Floorplanning. In Proc. ICCAD, pp.
809 1 100% 48.35 17.44 100% 34.34 5.51 74–80, 2003.
10 /786 2 0% — — 100% 33.80 5.68
/16334 3 0% — — 100% 35.29 5.39 [10] Y. Zhan, Y. Feng and S. S. Sapatnekar. A Fixed-Die
1124 1 100% 20.46 31.44 100% 22.44 7.42 Floorplanning Algorithm Using an Analytical Approach. In
11 /373 2 0% — — 100% 22.60 7.42 Proc. ASP-DAC, pp. 771–776, 2006.
/16985 3 0% — — 100% 23.04 7.43
582 1 0% — — 100% 30.72 3.42 [11] J. Cong, M. Romesis and J. R. Shinnerl. Fast Floorplanning by
12 /651 2 0% — — 54% 32.60 10.38 Look-Ahead Enabled Recursive Bipartitioning. In Proc.
/11873 3 0% — — 100% 31.74 2.65 ASP-DAC, pp. 1119–1122, 2005.
530 1 0% — — 100% 26.86 5.43
13 /424 2 100% 43.63 10.05 100% 26.93 5.18 [12] M. Lai, and D. F. Wong. Slicing Tree Is a Complete Floorplan
/14202 3 0% — — 100% 27.41 5.18 Representation. In Proc. DATE, pp. 228–232, 2001.
1021 1 100% 78.82 38.42 100% 51.87 8.46 [13] G. Karypis and V. Kumar. Multilevel K-way Hypergraph
14 /614 2 100% 58.57 36.94 100% 52.42 8.45
/26675 3 100% 63.48 33.22 100% 54.13 8.45 Partitioning. In Proc. DAC, pp. 343–348, 1999.
1019 1 0% — — 100% 64.39 10.22 [14] L. Stockmeyer. Optimal orientations of cells in slicing
15 /393 2 0% — — 100% 63.98 10.23 floorplan designs. In Information and Control , vol. 57, pp.
/28270 3 0% — — 100% 65.18 10.21
633 1 0% — — 100% 55.98 6.16 91–101, 1983.
16 /458 2 100% 88.57 15.57 100% 57.43 6.66 [15] GSRC Floorplan Benchmarks.
/21013 3 100% 97.47 21.97 100% 58.05 6.23 http://vlsicad.eecs.umich.edu/BK/GSRCbench/
682 1 100% 99.38 43.90 100% 96.63 8.90
17 /760 2 100% 94.26 55.32 100% 96.91 8.90 [16] HB Floorplan Benchmarks.
/30556 3 100% 101.23 50.79 100% 99.33 8.90 http://cadlab.cs.ucla.edu/cpmo/HBsuite.html
658 1 100% 53.78 33.00 100% 49.46 6.73
18 /285 2 100% 49.04 39.10 100% 49.54 6.73
/21191 3 100% 51.86 39.09 100% 51.25 6.73
Norm 0.450 1.26 3.85 1 1 1

Table 3: Comparison with PATOMA on HB Benchmarks.

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