App lica tion No te , V 1.0, June.

2005

AP32091

EMC
Design Guideline for
TC1766
Microcontroller
Board Layout

M i c ro c o n trollers

N e v e r s t o p t h i n k i n g .
EMC

Revision History: 2005-06 V 1.0

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Controller Area Network (CAN): License of Robert Bosch GmbH

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview

Table of Contents Page

1 Overview .................................................................................................................................... 4
1.1 General Informations:................................................................................................................. 4
1.2 Pinout of TC1766 ....................................................................................................................... 4
1.3 PCB Design Recommendations ................................................................................................. 4
1.4 Decoupling ................................................................................................................................. 7

Application Note 3 V 1.0, 2005-06

 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview
1 Overview
The TC1766 is a 32-Bit microcontroller in LQFP 176-pin package, which requires a carefully designed PCB concerning
electromagnetic compatibility. In additional to the Infineon PCB Design Guidelines for Microcontrollers (AP2426), which
gives general design rule informations for PCB design, some product-specific recommendations and guidelines for TC1766
are discussed here.

1.1 General Informations:

The microcontroller has two supply domains (1.5V Core / 3.3V I/O Pad), which should be decoupled individually.
The power supply feeding from the regulator outputs to each domain can be made on a supply layer (POWER).

1.2 Pinout of TC1766

TC1766

VSS VDD VDDP

Figure 1 Pinout of TC1766 (Supply pins colored to show the position):

1.3 PCB Design Recommendations

„ To minimize the EMI radiation on the PCB, following signals have to be considered as critical. Route these signals
with adjacent ground reference and use as less as possible vias (no reference layer change!) route them as short
as possible. Routing ground on each side can help to reduce coupling to the other signals.
– TCLKO and SYSCLK: Transmit channel clock output/ System clock output
– Supply pins

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview
„ For unused “Output, Supply, Input and I/O “ pins following points must be considered:

1. Supply Pins (Modules) : - See product specification

2. I/O-Pins: - must be configured as output and driven to static low in the weakest
driver mode.
- solderpad should be left open and not be connected to any other net
(layout isolated PCB-pad only for soldering)
3. Output Pins including LVDS: - should be driven static in the weakest driver mode.
- if static output level is not possible, the output driver should be disabled.
- solderpad should be left open and not be connected to any other net
(layout isolated PCB-pad only for soldering)
4.Input Pins without internal pull device: - For pins with alternate function see product target specification to define
the necessary logic level
- must be connected with high-ohmic resitor to GND (range 10k – 1Meg)
- groups of 8 pins can be used to reduce number of external pull-up/down
devices (keep in mind leakage current)
5. Input Pins with internal pull device: - For pins with alternate function see product specification to define the
necessary logic level
- must be configured as Pull-down and should activated static low
(exception: if the product specification requires high level for alternate
functions)
- solderpad should not be connected to any other net (isolated PCB-pad
only for soldering)

„ The ground system must be designed as follows:

- Separate of analog and digital grounds.
- The analog ground must be separated into three groups:
1. Ground for OSC (104),
2. Ground for ADC0/1 (53),
3. Ground for FADC (22,25)
„ To reduce the radiation / coupling from oscillator circuit, a separated ground island on the GND layer should be
made. This ground island can be connected at one point to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The ground connections of the load capacitors and VSSOSC
should also be connected to this island. Traces for load capacitors and Xtal should be as short as possible.
„ The power distribution from the regulator to each power plane should be made over filters (EMI filter using ferrite
beads).
„ A target inductance value of <2nH (VDDC), <1nH (VDDP) for the connection of decoupling capacitors to the supply
pins is required.
„ Inductance/Ferritebeads on supply paths L ~10µH /1A (at regulator output and at the branching to the other module
supply pins like VDDOSC, VDDOSC3, VDDFL3…see Figure 2).
„ OCDS must be disabled.
„ Select weakest possible driver.
„ Use for SYSCLOCK lowest possible frequency.
„ Avoid to cut the GND plane through via groups. A solid GND plane must be designed.

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview

Connectionof VDDOSC, VDDOSC3 and VDDFL3:

1.5V 3.3V

Ferrite Bead or Inductor Ferrite Bead or Inductor

VDDOSC VDDOSC3

µC
47nF
47nF

Ferrite Bead or Inductor

VDDFL3

47nF //47nF

Figure 2 Filtering of VDDOSC, VDDOSC3 and VDDFL3 supply pins

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview

1.4 Decoupling
„ All two supply domains of TC1766 should be decoupled separately (see decoupling layout example)
„ Type of capacitors:
– Values: 10nF, 47nF, 100nF
– X7R Ceramic Multilayer (Low ESR and low ESL)
„ All supply pins should be connected first to the dedicated decoupling capacitor and then from the capacitors over
vias to the power planes.
„ All VSS pins should be connected to the GND layer (see layout example on next figure).
„ The decoupling capacitors should be placed directly under the IC or if neccesary, some capacitors can be placed
on top layer close to the supply pins of the IC.
„ Ground plane on bottom layer can be used to connect the capacitors If no plane is used, they should be connected
with vias to the GND layer.
„ Multiple vias can be used at capacitors to get a low impedance connection between capacitors and power/GND
planes or pins.
„ All capacitors must be placed as close as possible to the related supply pin group.
A power-plane/grounding concept example for a 32-bit microcontroller with LQFP package can be seen in figure 3. This
layout example shows two supply domains (1.5V, 3.3V), where 1.5V is core supply and 3.3V is pad supply voltage.

Capacitors on bottom layer

Signal/GND
GND
Power
Signal

Optional: Capacitors for double sided placement

VDDP on Power- layer

Gnd isle for

Oscillator

VDD on Power-layer

From VR GND

Figure 3 Layout example for decoupling of TC1766

The general way is to connect the VDD and GND first to the capacitors and then connect to the pins of the IC. The GND and
VDD supply planes are on the second and third layer.

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview

VSS Via/connection to GND

CAP
VDDP CAP Via/connection to VDDP

VDD Via/connection to VDD

µC

Figure 4 Connection of decoupling capacitors

Decoupling Capacitor List:

CapacitorType Supply Pins
100nF X7R VDD 68
100nF X7R VDD 84
100nF X7R VDD 99
100nF X7R VDD 99
100nF X7R VDD 153
100nF X7R VDD 10
47nF X7R VDD 68
47nF X7R VDD 84
47nF X7R VDD 99
47nF X7R VDD 123
47nF X7R VDD 153
47nF X7R VDD 170
10nF X7R VDDP 83
10nF X7R VDDP 124
10nF X7R VDDP 139
10nF X7R VDDP 154
10nF X7R VDDP 171
10nF X7R VDDP 11
47nF X7R VDDP 69
47nF X7R VDDP 100
10nF X7R VDDAF 23
10nF X7R VDDM 54
10nF X7R VDDMF 24
47nF X7R VDDOSC 105
47nF X7R VDDOSC3V3 106
47nF X7R VDDFL3 141
47nF X7R VDDFL3 141

Total= 6 x 100nF, 12 x 47nF, 9 x 10nF

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 AP32091
Design Guideline for TC1766 Microcontroller Board Layout
Overview

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Application Note 9 V 1.0, 2005-06