CSE141L

Based on the given requirements, here is a possible specification for your Instruction Set
Architecture (ISA):

1. Operations and Opcodes:

- The ISA supports the following operations: add, subtract, bitwise AND, bitwise OR, bitwise
XOR, load, store, branch if equal, branch if not equal.
- The opcodes for each operation are as follows:
- Add: 000
- Subtract: 001
- Bitwise AND: 010
- Bitwise OR: 011
- Bitwise XOR: 100
- Load: 101
- Store: 110
- Branch if equal: 111 (condition is met if two operands are equal)
- Branch if not equal: 111 (condition is met if two operands are not equal)

2. Instruction Formats:
- The ISA supports two instruction formats: R-format and I-format.

R-format:
- 3 bits for the opcode
- 3 bits for the source register A
- 3 bits for the source register B
- The result is stored in the destination register

I-format:
- 3 bits for the opcode
- 3 bits for the source register
- 3 bits for the immediate value (used for data or branch target address)

3. Registers:
- The ISA has a total of 8 registers.
- 6 general-purpose registers (R0-R5).
- 2 specialized registers (Instruction Pointer and Flags Register).
- The specialized registers are not directly accessible but are used internally for program
control and flags.

4. Internal Data Paths and Storage:

- All internal data paths and storage are 8 bits wide.

5. Addressing Modes:
- For memory instructions:
 - Load: Direct addressing mode using an 8-bit address pointer.
- Store: Direct addressing mode using an 8-bit address pointer.
- For branch instructions:
- Branch if equal/branch if not equal: Immediate addressing mode for the branch target
address.

Please note that this is just one possible specification based on the given requirements. You can
modify and refine it as per your design choices and specific program requirements.

Program1:
To generate the corresponding 16-bit encoded versions for the given series of 11-bit message
blocks, you can use the provided input and output formats. Here's the step-by-step process:

1. Start with the first message block, mem[0], which contains the lower 8 data bits: b8 b7 b6 b5
b4 b3 b2 b1.

- p8 = ^(b11:b5) = ^(0 b11 b10 b9 b8 b7 b6 b5) = b11 ⊕ b10 ⊕ b9 ⊕ b8 ⊕ b7 ⊕ b6 ⊕ b5.

2. Calculate the parity bits:

- p4 = ^(b11:b8, b4, b3, b2) = ^(0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2) = b11 ⊕ b10 ⊕ b9 ⊕ b8 ⊕
b4 ⊕ b3 ⊕ b2.
- p2 = ^(b11, b10, b7, b6, b4, b3, b1) = ^(0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1) = b11 ⊕ b10
⊕ b7 ⊕ b6 ⊕ b4 ⊕ b3 ⊕ b1.
- p1 = ^(b11, b9, b7, b5, b4, b2, b1) = ^(0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1) = b11 ⊕ b9 ⊕
b7 ⊕ b5 ⊕ b4 ⊕ b2 ⊕ b1.
- p0 = ^(b11:1, p8, p4, p2, p1) = ^(0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p8 p4 p2 p1) = b11 ⊕
b10 ⊕ b9 ⊕ b8 ⊕ b7 ⊕ b6 ⊕ b5 ⊕ p8 ⊕ p4 ⊕ p2 ⊕ p1.

3. Construct the encoded version:

- MSW = b11 b10 b9 b8 b7 b6 b5 p8.
- LSW = b4 b3 b2 p4 b1 p2 p1 p0.

4. Store the encoded version in data mem[30:59]:

- mem[30] = LSW (bits b4:b2, p4, b1, p2:p1, p0).
- mem[31] = MSW (bits b11:b5, p8).

Repeat the above steps for each of the fifteen 11-bit message blocks, updating the memory
locations accordingly.
Program2:
To recover the original message from the series of 15 two-byte encoded data values in data
mem[30:59], you can use the provided coding scheme that can correct any single-bit error and
detect any two-bit error. Here's the step-by-step process:

1. Start with the first encoded data value in mem[30] and mem[31]. This corresponds to the
MSW and LSW of the encoded value.

2. Extract the bits according to the given format:

- F1 = MSW bit b11.
- F0 = MSW bit b10.
- D11 = MSW bit b9.
- D10 = MSW bit b8.
- D9 = MSW bit b7.
- D8 = MSW bit b6.
- D7...D0 = LSW bits b7...b0.

3. Check the values of F1 and F0 to determine the error status:

- If F1F0 = 00, there are no errors.
- If F1F0 = 01, there is one error (either in data or parity).
- If F1F0 = 1X, there are two errors.

4. If there are no errors (F1F0 = 00), store the extracted bits in the corresponding memory
locations in mem[0:29] as follows:
- mem[0] = D11.
- mem[1] = D10.
- mem[2] = D9.
- mem[3] = D8.
- mem[4] = D7.
- mem[5] = D6.
- mem[6] = D5.
- mem[7] = D4.
- mem[8] = D3.
- mem[9] = D2.
- mem[10] = D1.
- mem[11] = D0.

5. If there is one error (F1F0 = 01), you need to correct the error. Determine the bit position of
the error by converting the binary value of F1F0 to decimal (e.g., F1F0 = 01 corresponds to an
error in the least significant bit).

6. Correct the error by flipping the bit at the error position. For example, if the error position is
5, flip the value of mem[4].
7. Store the corrected bits in the corresponding memory locations in mem[0:29] as described in
step 4.

8. If there are two errors (F1F0 = 1X), you only need to set F1 to 1 to indicate the presence of
two errors. The exact error positions or values cannot be recovered, so no further action is
required.

9. Repeat steps 2-8 for each of the 15 encoded data values, updating the memory locations
accordingly.

Note: The exact number of possible inputs for each of the 2^11 possible outputs depends on
the specific coding scheme used, which is not provided in the question.

Program3:
1. Initialize necessary counters
2. Extract 5-bit pattern from data_mem[32]
3. Iterate from data_mem[0] to data_mem[31]
4. Iterate through each byte within (0 to 7)
5. Compare the 5 bits with the 5-bit pattern
6. If found, break loop and increment counter1
7. If counter1>0, counter2++
8. Counter3 = counter3 + counter1
9. Data_mem[33] = counter1
10. Data_mem[34] = counter2
11. Data_mem[35] = counter3
12. Repeat 3-11 for full message

Milestone 1:
Milestone 1 Components:

1. Introduction:
- Architecture Name: "FlexiCore"
- Overall Philosophy: FlexiCore aims to provide a flexible and versatile processor architecture
that can efficiently handle a wide range of computational tasks.
- Specific Goals:
- High performance through parallelism and efficient instruction execution.
- Support for various addressing modes and memory operations.
- Compact instruction set for code density.
- Support for error detection and correction in communication protocols.
- Classification: FlexiCore belongs to the register-based architecture class.

2. Architectural Overview:
- Major Building Blocks:
 - Instruction Fetch Unit (IFU): Fetches instructions from memory.
- Instruction Decode Unit (IDU): Decodes instructions and identifies their formats.
- Register File: Stores general-purpose registers.
- Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations.
- Memory Unit: Handles memory operations (load/store).
- Control Unit: Controls the execution flow and handles branching and control signals.

3. Machine Specification:
- Instruction Formats:
- Format 1: Register-Immediate (RI)
- Example: ADDI R1, R2, #10
- Format 2: Register-Register (RR)
- Example: ADD R1, R2, R3
- Format 3: Branch (B)
- Example: BEQ R1, R2, label
- Operations:
- ADD: Addition of two register values
- ADDI: Addition of a register and an immediate value
- BEQ: Branch if two registers are equal
- Internal Operands:
- General-purpose registers: R0-R7
- All registers are general-purpose and have no special functionality.
- Control Flow (Branches):
- Types: Conditional branch (BEQ)
- Target addresses are calculated based on the branch instruction and the offset specified.
- Maximum branch distance supported: ±2047 instructions (12-bit signed offset).
- Addressing Modes:
- Supported Modes: Direct addressing
- Addresses are calculated directly using the immediate or register values specified in the
instruction.

4. Programmer's Model [Lite]:

- FlexiCore operates as a register-based architecture, where computations are performed
using registers.
- Assembly Language Instruction Example: ADDI R1, R2, #10 (Add immediate)
- Corresponding Machine Code: 00110001 00010010 00000010 00000010 (Example values in
binary)
- Opcode (6 bits): 001100 (ADDI)
- Destination Register (3 bits): 001 (R1)
- Source Register (3 bits): 000 (R2)
- Immediate Value (8 bits): 00000010 (10 in decimal)

Program1:
# Program 1 - Forward Error Correction Block Coder/Transmitter
# Initialize data memory addresses
MSW_INPUT_ADDR = 0
LSW_INPUT_ADDR = 1
MSW_OUTPUT_ADDR = 30
LSW_OUTPUT_ADDR = 31

# Iterate over the fifteen 11-bit message blocks

FOR i = 0 TO 14:
# Read MSW and LSW of the input message block
MSW_INPUT = data[MSW_INPUT_ADDR + i * 2]
LSW_INPUT = data[LSW_INPUT_ADDR + i * 2]

# Calculate parity bits

p8 = ~(MSW_INPUT[4:0]) # Parity bit 8
p4 = ~(MSW_INPUT[7:0] + LSW_INPUT[7:2]) # Parity bit 4
p2 = ~(MSW_INPUT[9:8] + MSW_INPUT[6:5] + LSW_INPUT[5:4] + LSW_INPUT[2] +
LSW_INPUT[0]) # Parity bit 2
p1 = ~(MSW_INPUT[9] + MSW_INPUT[7] + LSW_INPUT[7] + LSW_INPUT[5] + LSW_INPUT[4] +
LSW_INPUT[2] + LSW_INPUT[1]) # Parity bit 1
p0 = ~(MSW_INPUT[9:1] + p8 + p4 + p2 + p1) # Parity bit 0

# Assemble the encoded message block

MSW_OUTPUT = MSW_INPUT[10:5] + p8
LSW_OUTPUT = LSW_INPUT[6:4] + p4 + LSW_INPUT[1] + p2 + p1 + p0

# Store the encoded message block in data memory

data[MSW_OUTPUT_ADDR + i * 2] = MSW_OUTPUT
data[LSW_OUTPUT_ADDR + i * 2] = LSW_OUTPUT
ENDFOR

Program2:
# Program 2 - Forward Error Correction Block Decoder

# Initialize data memory addresses

INPUT_ADDR = 0
OUTPUT_ADDR = 60

# Iterate over the 2^11 possible outputs

FOR i = 0 TO 2047:
# Read the input data
INPUT = data[INPUT_ADDR]

# Initialize error counters

 data_error_count = 0
parity_error_count = 0

# Calculate the parity bits for the input data

p8 = ~(INPUT[7:3]) # Parity bit 8
p4 = ~(INPUT[10:4]) # Parity bit 4
p2 = ~(INPUT[10:5] + INPUT[2] + INPUT[0]) # Parity bit 2
p1 = ~(INPUT[10] + INPUT[8] + INPUT[6] + INPUT[4] + INPUT[2] + INPUT[0]) # Parity bit 1
p0 = ~(INPUT[10:1] + p8 + p4 + p2 + p1) # Parity bit 0

# Compare the calculated parity bits with the input parity bits
IF INPUT[9:8] != p8:
parity_error_count += 1
ENDIF
IF INPUT[7:6] != p4:
parity_error_count += 1
ENDIF
IF INPUT[5:3] != p2:
parity_error_count += 1
ENDIF
IF INPUT[2:1] != p1:
parity_error_count += 1
ENDIF
IF INPUT[0] != p0:
parity_error_count += 1
ENDIF

# Count the number of data bit errors

FOR j = 10 TO 0:
IF INPUT[j] != ~(p8 + p4 + p2 + p1 + p0) AND INPUT[j] != p8 AND INPUT[j] != p4 AND
INPUT[j] != p2 AND INPUT[j] != p1 AND INPUT[j] != p0:
data_error_count += 1
ENDIF
ENDFOR

# Determine the error status and set F1F0 bits accordingly

IF parity_error_count == 0 AND data_error_count == 0:
F1F0 = 0 0 # No errors
ELSEIF data_error_count == 1 OR parity_error_count == 1:
F1F0 = 0 1 # One error (data or parity)
ELSE:
F1F0 = 1 X # Two errors
ENDIF
 # Store the original message along with the error status in data memory
data[OUTPUT_ADDR] = F1F0 0 0 0 INPUT[10:0]

# Increment the data memory address for the next iteration

OUTPUT_ADDR += 1
ENDFOR

Program3:
# Program 3 - Pattern Search

# Initialize data memory addresses

MESSAGE_ADDR = 0
PATTERN_ADDR = 32
TOTAL_OCCURRENCES_ADDR = 33
BYTES_WITHIN_PATTERN_ADDR = 34
TOTAL_COUNT_ADDR = 35

# Read the message string and pattern from data memory

MESSAGE = data[MESSAGE_ADDR:MESSAGE_ADDR+31]
PATTERN = data[PATTERN_ADDR:PATTERN_ADDR+4]

# Initialize counters
total_occurrences = 0
bytes_within_pattern = 0
total_count = 0

# Iterate over each byte in the message string

FOR i = 0 TO 31:
byte = MESSAGE[i]

# Count the occurrences of the pattern within the current byte

occurrences = 0
FOR j = 7 TO 3:
IF byte[j-4:j] == PATTERN:
occurrences += 1
ENDIF
ENDFOR

# Update the total number of occurrences

total_occurrences += occurrences

# Check if the current byte contains at least one copy of the pattern
IF occurrences > 0:
bytes_within_pattern += 1
 ENDIF

# Update the total count considering the possibility of pattern spanning adjacent bytes
IF i != 31:
IF byte[7:3] + MESSAGE[i+1][2:0] == PATTERN:
total_count += 1
ENDIF
ENDIF
ENDFOR

# Store the results in data memory

data[TOTAL_OCCURRENCES_ADDR] = total_occurrences
data[BYTES_WITHIN_PATTERN_ADDR] = bytes_within_pattern
data[TOTAL_COUNT_ADDR] = total_count

Program 1 assembly:
# Declare variables for parity bits
.data
p0: .word 0
p8: .word 0
p4: .word 0
p2: .word 0
p1: .word 0

# Declare array for encoded messages

encoded_msg: .space 16

# Main program
.text
main:
# Initialize variables
li $t0, 0 # i = 0

# Loop for encoding each message block

loop:
slti $t1, $t0, 15 # Check if i < 15
beqz $t1, done # If i >= 15, exit the loop

# Calculate parity bits

lw $t2, d1_in($t0) # Load d1_in[i] from memory
srl $t3, $t2, 5 # Extract bits [11:5]
xor $t4, $t3, $t3 # Calculate p8
xori $t5, $t2, 0xFFE0 # Extract bits [11:8] and [4:2]
xor $t5, $t5, $t5 # Calculate p4
srl $t6, $t2, 1 # Extract bit 1
xor $t6, $t6, $t2 # Extract bits [11], [10], [7], [6], [4], [3], and [1]
xor $t6, $t6, $t6
xor $t7, $t2, $t2 # Calculate p2
 xor $t7, $t7, $t7
xor $t8, $t2, $t2 # Calculate p1
xor $t8, $t8, $t8
xor $t9, $t2, $t2 # Calculate p0

# Store parity bits in memory

sw $t4, p8 # Store p8
sw $t5, p4 # Store p4
sw $t7, p2 # Store p2
sw $t8, p1 # Store p1
sw $t9, p0 # Store p0

# Assemble the encoded output

sll $t3, $t3, 5 # Shift p8 to its position
sll $t5, $t5, 2 # Shift p4 to its position
sll $t8, $t8, 1 # Shift p2 to its position
sll $t9, $t9, 0 # Shift p1 to its position
sll $t9, $t9, 0 # Shift p0 to its position
or $t10, $t3, $t5 # Combine d1_in[i][11:5] and p8
or $t11, $t10, $t5 # Combine above result with d1_in[i][4:2] and p4
or $t12, $t11, $t8 # Combine above result with d1_in[i][1] and p2
or $t13, $t12, $t9 # Combine above result with p1 and p0
sw $t13, encoded_msg # Store the encoded message

# Increment i
addi $t0, $t0, 1
j loop

done:
# Set the done signal to indicate completion
li $t0, 1
sw $t0, done

# Exit the program

li $v0, 10
syscall