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    mosfet_intro

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    of 46

    Electronic Circuit I

    MOSFETS

    EEG 331: ELECTRONIC CIRCUITS I


    Learning Outcome

    Understand the following


    • Historical background
    • Physical structure of MOSFET
    • Qualitative operations,
    • MOSFET Symbols,
    • IV Characteristics

    EEG 331: ELECTRONIC CIRCUITS I


    Some Transistor History

    EEG 331: ELECTRONIC CIRCUITS I


    EEG 331: ELECTRONIC CIRCUITS I
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    EEG 331: ELECTRONIC CIRCUITS I
    MOSFET: Introduction
    ✓ Metal Oxide Semiconductor Field Effect Transistor
    ✓ Became practical reality in 1970s
    ✓ Can be integrated much smaller on a chip
    ✓ Basic building block of digital circuits such as
    memories and processors
    ✓ Can also be used in analog circuits

    EEG 331: ELECTRONIC CIRCUITS I


    EEG 331: ELECTRONIC CIRCUITS I
    MOS Capacitor Structure

    Simplest MOS device is the MOS capacitor with just two terminals
    MOS transistor (MOSFET) has four terminals

    EEG 331: ELECTRONIC CIRCUITS I


    MOS capacitor operation

    • MOS can be compared to parallel plate capacitor


    • Top electrode is called gate while the bottom is the substrate
    • Applying a negative gate bias leads to accumulation of holes at the semiconductor
    - oxide interface

    EEG 331: ELECTRONIC CIRCUITS I


    MOS capacitor operation (Contd)

    • Applying a positive gate bias to same structure leads to depletion of holes (a)
    from the interface towards the substrate
    • Positive charges are repelled to the gate by the electric field
    • Induced space-charge region (no +ve mobile charges but –ve immobile ions)
    is created in the substrate – oxide interface (b)
    • As the positive gate bias increases, free electrons appears in the space charge region (c)
    which is referred to as electron inversion layer

    EEG 331: ELECTRONIC CIRCUITS I


    MOS Operation Summary
    For p – substrate, negative gate bias leads to accumulation of holes in
    the semiconductor while positive gate bias creates a depletion region
    and inversion region in the substrate

    For n – substrate, positive gate bias leads to accumulation of electrons


    in the semiconductor while negative gate bias creates a depletion
    region and inversion region in the substrate

    EEG 331: ELECTRONIC CIRCUITS I


    N-channel Enhancement Mode
    MOSFET Terminals:
    Source, Gate, Drain and
    Substrate

    Recall that an inversion region is


    created in MOS capacitor below
    the oxide with a positive gate bias
    , this is called channel region

    Usually, conduction occurs during


    the inversion region because
    electrons flows from the source
    to drain

    Channel length L and Width are


    typically less than 1 micrometer

    Oxide thickness tox are is less


    than 40 nm

    EEG 331: ELECTRONIC CIRCUITS I


    Circuit Symbols

    EEG 331: ELECTRONIC CIRCUITS I


    N-channel Enhancement Mode
    MOSFET : Operation
    • When zero voltage is applied to the gate, the source and drain region are separated
    by the p region.

    • When large enough positive voltage is applied to the gate, inversion layer is created
    (channel) in the p-region which connects the source to the drain.

    • Electrons can then move from the source to drain resulting to current flow

    • It is called enhancement mode because a voltage is required to create an inversion


    region

    • It is called N-channel because, the electrons contribute to flow of current

    • Ideally no current flows in the oxide and substrate because the oxide is an insulator
    and the channel is separated from the substrate by a space-charge region.

    EEG 331: ELECTRONIC CIRCUITS I


    MOSFET IV Characteristics

    VGS < VTH and positive VDS applied: Space charge regions created, transistor in OFF state
    essentially drain current is almost zero
    VGS > VTH and positive VDS applied:
    Inversion layer created, transistor turns ON, current flows in the device as VDS is increased

    EEG 331: ELECTRONIC CIRCUITS I


    EEG 331: ELECTRONIC CIRCUITS I
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    IV Curve – Id vs Vds

    EEG 331: ELECTRONIC CIRCUITS I


    𝑊
    Where 𝐾 = 𝐿 µ𝑛 𝑐𝑜𝑥
    This is a parameter which depends on device geometry width W, length L and oxide
    capacitance 𝑐𝑜𝑥

    EEG 331: ELECTRONIC CIRCUITS I


    EEG 331: ELECTRONIC CIRCUITS I
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    EEG 331: ELECTRONIC CIRCUITS I
    Simulation MOSFET

    EEG 331: ELECTRONIC CIRCUITS I


    Output Characteristics

    EEG 331: ELECTRONIC CIRCUITS I

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