Microprocessor 8086

Memory Write Operation

 1. The word to be stored into the memory location is first loaded

by the CPU into a specified register, called the memory data
register (MDR).
 2. The address of the location into which the word is to be
stored is loaded by the CPU into a specified register, called the
memory address register (MAR).
 3. A signal, called write, is issued by the CPU indicating that the
word stored in the MDR is to be stored in the memory location
whose address in loaded in the MAR.
Microprocessor 8086

 8086 microprocessor has a 16-bit data bus and 20-bit

address bus. So, it can address any one of 220 =1048576=1
megabyte memory locations
 INTEL 8088 has the same ALU, same registers and same
instruction set as the 8086.But the only difference is 8088
has only 8-bit data bus and 20-bit address bus. Hence the
8088 can only read/write/ports of only 8-bit data at a
time
Minimum mode and Maximum mode

 The 8086 microprocessor can work in two modes of

operations .
 They are Minimum mode and Maximum mode. In the
minimum mode of operation the microprocessor do not
associate with any co-processors and cannot be used for
multiprocessor systems. But in the maximum mode the
8086 can work in multi-processor or co-processor
configuration. This minimum or maximum operations are
decided by the pin MN/ MX.
 When this pin is high 8086 operates in minimum mode
otherwise it operates in Maximum mode
8086 Microprocessor features
 1. It is 16-bit microprocessor.
 2. It has a 16-bit data bus, so it can read data from or write data to memory and ports either 16-
bit or 8-bit at a time.
 3. It has 20 bit address bus and can access up to 220 memory locations (1 MB).
 4. It can support up to 64K I/O ports.
 5. It provides 14, 16-bit registers.
 6. It has multiplexed address and data bus AD0-AD15 & A16-A19.
 7. Pre-fetches up to 6 instruction bytes from memory and queues them in order to speed up the
processing.
 8. 8086 supports 2 modes of operation
 a. Minimum mode
 b. Maximum mode
Architecture of 8086 microprocessor

 To improve the performance by implementing the parallel

processing concept the CPU of the 8086 /8088 is divided
into two independent sections .
 They are Bus Interface Unit (BIU)
 and Execution Unit (EU) as shown in figure 2.
Architecture of 8086 Microprocessor
 Bus Interface Unit (BIU):
 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 the bus interface unit connects the microprocessor to external devices.
 BIU performs following operations:
 Instruction fetching.
 Reading and writing data of data operands for memory.
 Inputting/outputting data for input/output peripherals.

 And other functions related to instruction and data acquisition.

 To implement above functions, the BIU contains the segment registers, the instruction
pointer, address generation adder, bus control logic, and an instruction queue.
 .
Bus Interface Unit
 The BIU uses a mechanism known as an instruction stream
queue to implement pipeline architecture
 Execution Unit (EU)

 The Execution unit is responsible for decoding and executing all instructions.
 The EU consists of arithmetic logic unit (ALU), status and control flags,
general‐purpose registers, and temporary‐operand registers.
 The EU extracts instructions from the top of the queue in the BIU, decodes
them ,generates operands if necessary, passes them to the BIU and requests it
to perform the read or write by cycles to memory or I/O and perform the
operation specified by the instruction on the operands.
 During the execution of the instruction, the EU tests the status and control
flags and updates them based on the results of executing the instruction
Pipelining Architecture in 8086mp
 While the EU is decoding an instruction or executing an
instruction, which does not require use of the buses, the BIU
fetches up to six instruction bytes for the following instructions.
 The BIU stores these pre-fetched bytes in a first-in-first-out
register set called a queue.
 When the EU is ready for its next instruction from the queue
in the BIU. This is much faster than sending out an address to
the system memory and waiting for memory to send back the
next instruction byte or bytes.
Pipelining Architecture in 8086mp

 Except in the case of JMP and CALL instructions, where

the queue must be dumped and then reloaded starting
from a new address, this pre-fetch and queue scheme
greatly speeds up processing.
 Fetching the next instruction while the current
instruction executes is called pipelining.
Register Organization

 The 14 registers of 8086 microprocessor are categorized

into four groups. They are general purpose data registers,
Pointer & Index registers, Segment registers, Instruction
register, and Flag register as shown in the table below
Register Organization
1. General Purpose Registers:
 8086 CPU has 8 general purpose registers; these registers can be
divided into:
 a) Data registers: four 16 bits data registers
 b) Pointer and index registers: two 16 bits pointer registers and
two 16 bits index registers
 a) Data Registers: they are four registers (AX, BX, CX, and DX)
which used for arithmetic and data movement. Each register
can be addressed as either 16-bit or 8 bit value. Example, AX
register is a 16-bit register, its upper 8-bit is called AH, and its
lower 8-bit is called AL. Bit 0 in AL corresponds to bit 0 in AX
and bit 0 in AH corresponds to bit 8 in AX as shown in the figure
below.
 Accumulator register (AX): It is the accumulator register
because it is favored by the CPU for arithmetic
operations. Other operations are also slightly more
efficient when performed using AX.
 Base register: The BX register can hold the address of a
procedure or variable. Three other registers with this
ability are SI, DI and BP. The BX register usually contains a
data pointer used for based, based indexed or register
indirect addressing. BX register can also perform
arithmetic and data movement.
 Count register: The CX register acts as a counter for
repeating or looping instructions. These instructions
automatically repeat and decrement CX.
 Data register: DX In integer 32-bit multiply and divide
instruction the DX register contains high order word of the
resulting number. DX register can be used as a port
number in I/O operations.
b) Index and Pointer Register

 There are four 16-bits registers two serve as pointers and

two serve as indexes. These registers usually store offset
address used for addressing within the segment
Index and Pointer Register

 Source Index (SI): is a 16-bit register. SI is used for indexed, based indexed
and register indirect addressing. As well as source data address in string
manipulation instructions. Used in conjunction with DS register to point to
data locations in the data segment.
 Destination Index (DI) is a 16-bit register. Used with the ES register in string
operations. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation
instructions.
Index and Pointer Register

 Stack Pointer (SP): is a 16-bit register pointing to stack, it is used to

hold the address of the top of the stack. The stack is maintained as
LIFO with its bottom at the start of the stack segment (Specified by
the SS segment register). Unlike the SP register, the BP can be used
to specify the offset of other program segments.
 Base Pointer (BP): is a 16-bit register pointing to stack segment. It
is usually used by subroutine to locate variables that were passed on
stack by calling program. BP register is usually used for based, based
indexed or register indirect addressing.