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Mod 5

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smita palnitkar
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23 views6 pages

Mod 5

Uploaded by

smita palnitkar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity modncount is

Port ( clk : in STD_LOGIC;

clr : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (2 downto 0));

end modncount;

architecture Behavioral of modncount is

signal count: std_logic_vector(2 downto 0);

begin

process(clk)

begin

if (clr='1') then count <= "000";


elsif (rising_edge (clk)) then

if (count="100")

then count <= "000";

else

count<=count+ 1;

end if;

end if;

end process;

q<=count;

end Behavioral;

Testbench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY hhh IS

END hhh;
ARCHITECTURE behavior OF hhh IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT modncount

PORT(

clk : IN std_logic;

clr : IN std_logic;

q : INOUT std_logic_vector(2 downto 0)

);

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal clr : std_logic := '0';

--BiDirs

signal q : std_logic_vector(2 downto 0);

-- Clock period definitions

-- constant clk_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: modncount PORT MAP (

clk => clk,

clr => clr,

q => q

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for 10 ns;

clk <= '1';

wait for 10 ns;

end process;

-- Stimulus process

stim_proc: process

begin

clr<='1';

-- hold reset state for 100 ns.

wait for 20 ns;

clr<='0';

-- hold reset state for 100 ns.


wait for 20 ns;

-- hold reset state for 100 ns.

-- wait for 100 ns;

--

-- wait for clk_period*10;

-- insert stimulus here

wait;

end process;

END;

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