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Unit II MCQ

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44 views8 pages

Unit II MCQ

Uploaded by

ekauoaphpsvbabnqal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Which of the following has the fastest speed in the computer memory

hierarchy?
A) Cache C) Main memory B) Register in CPU D) Disk cache

How many types of modes of I/O Data Transfer?


A) 2 C) 4 B) 3 D) 5

The method which offers higher speeds of I/O transfers is


___________
A) Interrupts C) Program-controlled I/O B) Memory mapping D) DMA

The ________ circuit is basically used to extend the processor BUS


to connect devices.
A) Router C) Bridge B) Processor D) None

Which of the following is true about DMA?


A) DMA is an approach of performing data transfers in bulk between
memory and the external device without the intervention of the
processor.
B) The DMA controller acts as a processor for DMA transfers and
overlooks the entire process.
C) The DMA controller has 3 registers.
D) All of the above

Computer address bus is


A) Multidirectional
B) Bidirectional
C) Unidirectional
D) None of the above

Which of the following circuit is used to store one bit of data?


A) Flip Flip. B) Decoder C) Encoder D) Register
Micro program is
A) The name of a source program in micro computer
B) set of microinstructions that defines the individual operations
in response to a machine language instruction
C) a primitive form of macros used in assembly language
programming
D) a very small segment of machine code

The usual BUS structure used to connect the I/O devices is


___________
A) Star BUS structure
B) Multiple BUS structure
C) Single BUS structure
D) Node to Node BUS structure

To overcome the lag in the operating speeds of the I/O device and the
processor we use
A) Buffer Spaces B) Status Flags C) Interrupt Signals D) Exceptions

The method of synchronising the processor with the I/O device in


which the device sends a signal when it is ready is?
A) Exceptions B) Signal Handling C) Interrupts D) DMA

The process wherein the processor constantly checks the status flags
is called as ___________
A) Polling B) Inspection C) Reviewing D) Echoing

While using the direct mapping technique, in a 16 bit system the


higher order 5 bits are used for ________
A) Id C) Tag B) Word D) Block
The device which is allowed to initiate data transfers on the BUS at
any time is called _____
A ) BUS master C) BUS arbitrator B) Processor D) Controller

The number successful accesses to memory stated as a fraction is


called as _____
A) Access rate C) Hit rate B) Success rate D) Miss rate

______ BUS arbitration approach uses the involvement of the


processor.
A) Centralised arbitration C) Random arbitration B) Distributed
arbitration D) All of the mentioned

The DMA differs from the interrupt mode by __________


A) The involvement of the processor for the operation B ) The method
of accessing the I/O devices C) The amount of data transfer possible
D) None of the mentioned

In the following indexed addressing mode instruction, MOV 5(R1),


LOC the effective address is ______\
A ) EA = 5+R1 B) EA = R1 C) EA = [R1] D) EA = 5+[R1]

________ are the different type/s of generating control signals.


A) Hardwired B) Micro-instruction C) Micro-programmed D) Both
Micro-programmed and Hardwired

The instruction, Add #45,R1 does _______


A) Adds the value of 45 to the address of R1 and stores 45 in that
address
B) Adds 45 to the value of R1 and stores it in R1
C) Finds the memory location 45 and adds that content to that of R1
D) None of the mentioned

The PCI follows a set of standards primarily used in _____ PC’s.


A) Intel B) Motorola C) IBM D) SUN

A complete transfer operation over the BUS, involving the address


and a burst of data is called _____
A) Transaction
B) Transfer
C) Move
D) Procedure

In DMA transfers, the required signals and addresses are given by


the __________
A) ) Processor B) Device drivers C) DMA controllers D) The
program itself

The signal sent to the device from the processor to the device after
receiving an interrupt is ___________
A) Interrupt-acknowledge B) Return signal C) Service signal D)
Permission signal

To get the physical address from the logical address generated by


CPU we use ____________
A) ) MAR B) MMU C) Overlays D) TLB

The sampling process in speaker output is a ________ process


A) Asynchronous B) Synchronous C) Isochronous D) None of the
mentioned
_____ signal is sent by the initiator to indicate the duration of the
transaction.
A) FRAME# B) IRDY# C) TMY# D) SELD#

Processor circuits are controlled by timing signal called …………


signal.
A) MAR B) Program counter C) Clock D) ALU

Processor performance is controlled by ----------------


a)Clock rate b)edge rate C) Control rate d)Rate

Fetch Cycle is used to fetch ------- into the IR register


A) only Opcode B) Only Operand c) both Opcode & Operand
d) none of these

Disadvantage of single bus organization is ------


A) One bus is used B) two buses are used C) Only address bus is
used D) Only data bus is used

Hard wired control is faster than micro programmed control


A) true B) false C) same speed D) none of these

Cache memory is ------------------than RAM memory in terms speed


A) faster B) slower C) same speed D) none of these

MFC is used to inform completion of memory operation from


-------------Device
A) Addressed b) Control C) ALU D) Memory

A micro operation every bit of a register is a:


A) Constant B) Variable C) Both D) None
The memory bus is also referred as______:
A) Data Bus B) Address bus C) Memory Bus D) All of these

______operations are the results of I/O operations that are written in


the computer program:
A) Programmed I/O B) DMA C) Handshaking D) Strobe

In devices 2 status reporting signals are:


A) BUSY B) READY C) Both a & b D) None of these

The time required to complete one instruction is called:


A) Fetch time B) Execution time C) Control time D) All of these

Register are assumed to use positive-edge triggered _____:


A) Flip-flop B) Logics C) Circuit D) Operation

_________with which computers perform is way beyond human


capabilities:
A) Speed B) Accuracy C) Accuracy D) Versatility

The processing speed of a computer depends on the __________of


the system:
A) Clock speed B) Motorola C) Cyrix D) None of these

Each interaction b/w CPU and I/O module involves:


A) Bus arbitration B) Bus revolution C) Data bus D) Control signals

The beginning of the architecture of the Itanium processor took place


at ___.
A) Intel B) Microsoft C) Hewlett-Packard D) Dell
Consider the below-mentioned statements with respect to virtual
address mode.

1. ___ occur from resource conflicts when the hardware cannot


support all possible combinations of instructions in simultaneous
overlapped execution.
2. ___ occurs when an instruction depends on the result of previous
instruction in a way that is exposed by the overlapping of instructions
in the pipeline.
A) Structural hazards, Data hazards
B) Control hazards, Structural hazards
C) Cache miss, Hazard in the pipeline
D) Control hazards, Cache miss

Consider the following statements with respect to I/O performance


measures
1. Throughput is the average number of tasks completed by the
server over a period of time.
2. The two most common measures of I/O performance, used
currently, are throughput and response time.
A) 1- True, 2- True
B) 1- False, 2- False
C) 1- True, 2- False
D) 1- False, 2- True

The configuration, in which no difference between memory and I/O


devices is seen by the CPU, is referred to as __________
A) memory unit
B) memory mapped I/O
C) memory address register
D) Control unit
Performance of a computer is often measured in terms of:

A) Clock rate
C) FLOPS (Floating Point Operations Per Second)
B) MIPS (Million Instructions Per Second)
D) All of the above

Which of the following correctly describes the sequence of steps in


executing an instruction in the CPU?
A) Decode → Fetch → Execute → Write Back
B) Fetch → Decode → Execute → Write Back
C) Fetch → Execute → Decode → Write Back
D) Decode → Execute → Fetch → Write Back

Which of the following is a primary characteristic of semiconductor


RAM?
A) Non-volatile and high speed
B) Volatile and high speed
C) Non-volatile and low speed
D) Volatile and low cost

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