PIC18F to PIC24F Migration and Performance Enhancement Guide

INTRODUCTION CPU CORE

This document discusses the features of the PIC18F Note: This migration document details the tran-
and PIC24F architecture. It highlights the differences sition from PIC18F devices to PIC24F
and similarities of various peripherals and discusses devices. Please note that some features
the factors that need to be considered when migrating may not be available. Refer to the device-
from PIC18F to PIC24F. In addition, there have been specific data sheet for more details. The
many updates to the PIC18F architecture, one of the device data sheets and errata are
most notable being the addition of Direct Memory available for download from the Microchip
Access (DMA). This document notes the differences Worldwide Website at:
between the older devices (lacking DMA) and newer http://www.microchip.com.
devices (with DMA), both in relation to each other and
in relation to PIC24F when applicable. Although the PIC24F architecture is significantly different
from the PIC18F architecture, PIC24F MCUs can be
viewed as a natural extension of PIC18F devices. This
document will help ease migration concerns when mov-
ing from one family to the other. Most of the changes,
such as data bit width, instruction word size, instruction
clocking scheme, and stack and core registers, primarily
affect assembly-based programs. Other hardware
features have been added to enhance processing
performance. Changes are summarized in Table 1.

TABLE 1: CPU CORE FEATURE COMPARISON

Features All PIC18F Devices PIC24F Devices
Instruction Size 16 Bits 24 Bits
Instruction Clocking TCY = FOSC/4 TCY = FOSC/2
Working Registers 1 (W, WREG) 16 (W0-W15)
STATUS Registers One (STATUS) Two (STATUS and CORCON)
Stack Hardware, 32 Levels Software
Hardware Multiplier 8x8 17x17
Hardware Divider No Hardware Assisted Division Using DIV and
REPEAT
Bit Shifting/Rotation Single Bit, Left or Right, Rotation Only Barrel Shifting Up to 15 Bits, Left or Right,
Shift or Rotate
Program Space Visibility (PSV) No Yes

Migration Considerations the PIC18F and the PIC24F devices are handled auto-
matically by the compiler and do not affect programs
The primary consideration when migrating from written in C.
PIC18F to PIC24F is that the PIC24F core uses FOSC/2
as its instruction clock, as opposed to the FOSC/4
Differences Between PIC18F Devices
instruction clock of the PIC18F device. This effectively
doubles the instruction rate at the same input clock without DMA and PIC18F Devices with DMA
speed, but also changes the base clock used by many There are few differences in the core between older
peripherals that utilize the instruction clock as their and newer PIC18F devices that fundamentally change
basis. This frequency change needs to be accounted the migration path between them or to PIC24F devices.
for when migrating to ensure that peripherals function
as expected. Most other changes in the CPU between

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MEMORY MAP AND PROGRAM The organization of the space and the location of non-
program memory features also differ somewhat, and
MEMORY
must be considered when porting an application. The
Both PIC18F and PIC24F architectures use the same key differences between the memory organization of
general schema for their program memory spaces. PIC18F and PIC24F devices are presented in Table 2.
Aside from the self-evident differences in width,
PIC24F devices also incorporate a larger addressing
range and enhanced visibility features in data space.

TABLE 2: MEMORY ORGANIZATION FEATURE COMPARISON

Features PIC18F without DMA PIC18F with DMA PIC24F
Organization 16-Bit, Byte Addressable 16-Bit, Byte Addressable 24-Bit, Word Addressable
Total Addressable Range 4 Mbytes (22-bit magnitude) 4 Mbytes (22-bit magnitude) 8 Mbytes (24-bit magnitude)
Maximum Available User 2 Mbytes (1FFFFFh) 2 Mbytes (1FFFFFh) 8 Mbytes (7FFFFFh)
Program Space (upper
boundary address)
Boot Block Support Most Devices Most Devices No
Interrupt/Reset/Trap Vectors 00h, 08h, 18h 00h, 08h, 18h (in Legacy mode), 00h to 1FFh
Controlled by IVTBASE
(in Vectored mode)
Configuration Word Locations 300000h to 30000Fh 300000h to 30FFFFh (whole In the Last Implemented
area is reserved, most devices Location of the Flash
have fewer Configuration Words) Program Memory
Device ID Locations 3FFFFEh and 3FFFFFh 3FFFFEh and 3FFFFFh FF0000h and FF0002h

Migration Considerations Differences Between PIC18F Devices

The first consideration is the size of the Program
without DMA and PIC18F Devices with DMA
Counter (PC). There are 22 bits for PIC18F devices and There are few differences in the program memory
24 bits for PIC24F devices. This largely affects applica- between older and newer PIC18F devices that funda-
tions that directly write to the Program Counter, as the mentally change the migration path between them or to
actual program memory sizes on these devices varies PIC24F devices.
from family to family and is not inherently larger on
PIC18F or PIC24F. The second consideration is that if
the PIC18F device does not support vectored interrupts,
it will have a much smaller reserved space for interrupts
than an equivalent PIC24F device (only locations 00h,
08h and 18h, on the PIC18F, with 00h to 1FFh on
PIC24F devices). A final consideration is that while most
PIC18F devices have hardware support for a dedicated
boot block (with separate write/code-protect controls for
this section), PIC24F devices do not.

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DATA MEMORY SPACE

TABLE 3: DATA MEMORY SPACE FEATURE COMPARISON

Features PIC18F without DMA PIC18F with DMA PIC24F
Addressing Range (size) 12 Bits 14 Bits 16 Bits
(4,096 bytes maximum) (16,384 bytes maximum) (65,536 bytes maximum)
Segmentation Linear Range, Banked Linear Range, Banked Linear Range,
Addressing; Linear Addressing Addressing; Linear Addressing No Segmentation
for Some Instructions for Some Instructions
Special Access Areas Access RAM (bottom of Access RAM (bottom of Near Data Space (bottom 8k)
lowest bank, top of highest lowest bank, top of highest
bank) bank)
SFR Location Top n Banks (depending on Top n Banks (depending on Distributed throughout Near
number of peripherals/SFRs) number of peripherals/SFRs) Memory
Stack Hardware, 32 Levels Deep, Hardware, 32 Levels Deep, Soft Stack Starting at 0800h,
Not Mapped in Memory Not Mapped in Memory Space User-Configurable End of
Space Stack
Data Access Byte (direct or indirect) Byte (direct or indirect) Double Word, Word or Byte
(all direct or indirect)
Hardware PSV No No Yes, Into Top Half of
Data Space

Address Range and Segmentation SFR LOCATIONS

Older PIC18F devices have a data memory space with In PIC18F architecture, all SFRs are located at the very
a 12-bit address range. In theory, the data space has a top of data memory as a more or less contiguous block
linear range and can be addressed directly by several (actual addresses depend on the device in question; as
of the PIC18F instructions. For the most part, however, previously mentioned, newer devices have a larger
the data space functions as a segmented space. Since data range). In PIC24F architecture, SFRs reside in the
most PIC18F instructions can only contain the eight lowest 2 Kbytes of the memory space, from addresses,
lower bits of a data address, the data space is effec- 0000h through 07FFh.
tively divided into 16 banks of 256 bytes each. The
exact memory location is also determined by the Bank SPECIAL ACCESS AREAS
Select Register (BSR), which contains the upper four The effective segmentation of the PIC18F data space
bits of the address. The entire range of the data space makes it necessary for some way of accessing SFRs
is 4 Kbytes, of which some or all, may be implemented and critical application data quickly. This is done by
as data RAM. creating a virtual data space bank, known as the
Some newer PIC18F devices have a data memory Access RAM, which is composed of the lower half of
space with a 14-bit address range. They act similarly to the lowest bank and the upper half of the upper bank.
older PIC18F devices, with the exception that there are This scheme makes certain that the SFR space is
up to 64 banks of 256 bytes, and a 6-bit BSR instead of always available, regardless of the contents of the
a 4-bit one. Similarly, this puts the entire range of the BSR. Use of the Access RAM is included as an argu-
data space at 16 Kbytes instead of 4 Kbytes. ment in PIC18F assembly language and is hard-coded
in the instruction’s opcode. In the PIC24F data space,
In contrast, the PIC24F data space is implemented as the first 8 Kbytes of data RAM, between the addresses
a single linear range of addresses. Most instructions of 0000h and 1FFFh, are referred to as the Near Data
can directly access any address within the first Space. Addresses in this space, including all SFRs, are
8 Kbytes of the range without the use of bank selection. accessible directly from all Direct Memory Access
The entire data space range is 64 Kbytes. Of this, only (DMA) instructions.
the first 32 Kbytes are implementable as data RAM; the
upper 32 Kbytes are a virtual memory space that is
used for PSV (see “Program Space Visibility (PSV)”
on page 4). The differences between the data memory
organization of PIC18F and PIC24F devices are
presented in Table 3.

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PROGRAM SPACE VISIBILITY (PSV) DATA ACCESS
Both PIC18F and PIC24F architectures allow for the PIC18F architecture can only work with data in terms of
direct access of information stored in the program bytes. In contrast, the PIC24F data space, organized in
memory space as data. For PIC18F, data from program 2-byte words, allows many instructions to work with
memory are read in the data space by the use of TBLRD data as bytes, words or double words (32 bytes). The
commands, with access being done on a word-by-word data type is determined by the argument used with the
basis. For PIC24F devices, program memory is also instruction.
made available through hardware-enabled Program
Space Visibility (PSV). When used, any 32 Kbyte
segment of the program space may be mapped into the
upper 32 Kbyte area of the data space on a read-only
basis. PSV uses a hardware register, PSVPAG, to
define which page of program memory will be mapped.
The PSV is controlled in software by the PSV bit
(CORCON).

PROGRAM STACK
As discussed in the “CPU Core” section on page 1,
PIC18F devices use a hardware stack for program flow
management. The stack is not memory-mapped and
has a fixed size of 32 levels, but the Top-of-Stack (TOS)
is mapped through the TOSU/H/L and STKPTR SFRs.
PIC24F architecture uses a stack implemented entirely
in mapped data space. The stack begins at 0800h in
Near Data Space, just outside of the SFR area, and
grows towards higher memory addresses using the
W15 register as a dedicated pointer. The size of the
stack is entirely user-defined with the SFR register,
SPLIM, which sets the address for stack overflow traps.

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INTERRUPT CONTROLLER
The PIC24F interrupt controller contains several expan-
sions on the legacy PIC18F. In addition, newer PIC18F
devices have added a “vectored interrupt” feature that
adds a number of increased user options for interrupts.
Table 4 summarizes the differences between the devices.

TABLE 4: INTERRUPT CONTROLLER FEATURE COMPARISON

PIC18F without
Features PIC18F with DMA PIC24F
DMA
Assignable Interrupt Priority High or Low High or Low 8 Levels, User-Defined
Interrupt Latency 3 or 4 TCY 2 TCY (vectored interrupts 5 TCY (fixed)
disabled) or 3 TCY (vectored
interrupts enabled)
Priority Exit from Sleep and Idle Modes No No Yes
Interrupt Nesting and Disable Option No No Yes
Software-Selectable Core Interrupt No(1) No(1) Yes
Priority Level (IPL)
Trap Vectors No No Yes (4)
Unique Interrupt/Trap Source No Yes, Interrupt Vector Table (IVT) Yes
Alternate Interrupt Vector Table No Yes, Vector Table Base Address Yes, Two Choices
(AIVT) is Fully Relocatable
Natural Priority Unmaskable or Non- No No Yes
Maskable Interrupts
Capable of Disabling Interrupts for a No No Yes
Specific Number of TCY
Note 1: A high-priority interrupt can interrupt a low-priority interrupt.

Unique PIC24F Interrupt Features Unsupported PIC18F Features

• User-Assignable Priority: Users can also give All interrupt features on PIC18F devices without DMA
each interrupt one of eight levels of priority, which are supported in the PIC24F interrupt controller. PIC18F
can be used to override the natural priority devices with DMA functionality have a relocatable
• Software-Assigned Core Priority: Users can Interrupt Vector Table base address that allows for more
also set a threshold priority level at which the control of the Interrupt Vector Table location than the
CPU will respond to interrupts PIC24F interrupt controller, which only has two options
• Interrupt Nesting: The use of natural priority and for the Interrupt Vector Table addresses.
user-assigned priority allows multiple interrupt
events to be nested; this feature can also be Non-Maskable Traps
selectively disabled In PIC24F architecture, there are four hardware trap
• Hard and Soft Traps: Up to eight non-maskable events with interrupts that can never be disabled:
hard traps with high natural priority are provided • Address Decode Error
to flag potentially serious events, such as math • Oscillator Failure
(divide-by-0), stack overflow/underflow, address • Stack Error
or data alignment and oscillator failure • Math (Overflow) Error
• Priority Exit from Power-Saving Modes: Allows
These errors always force an immediate jump to
the application to either resume normal code
specific interrupt vectors. The two most serious errors
execution or jump to an ISR, depending on the
(Address Decode and Oscillator Failure) are hard
Interrupt Priority Level
traps; these must be cleared before the CPU execution
Note: For further information on traps, refer to can continue. All traps have their own individual flag bit.
the specific device data sheet. In addition to these unmaskable events, the PIC24F
architecture can be expanded at a future time to
include up to four additional traps. PIC18F architecture
does not have an equivalent to the hardware trap.
PIC18F stack error events are treated as Resets.

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Bit Name Changes and Mapping Optional step:

PIC24F devices maintain the same general nomenclature Select the user-assigned priority level for the interrupt
for interrupt bit names as PIC18F devices, with two source by writing the control bits in the appropriate
important differences. Both families maintain interrupt IPCx register. The priority level will depend on the
enable, flag and priority bits that are generically named specific application and type of interrupt source. If
xxxIE, xxxIF and xxxIP (where ‘xxx’ is the mnemonic for multiple priority levels are not desired, the IPCx register
the interrupt source). The first major difference is the control bit for all enabled interrupt sources may be
presence of three interrupt priority bits for each source, programmed to the same non-zero value.
instead of the one used for PIC18F devices. These bits, Note: Upon Reset, all interrupts are assigned a
generically named xxxIP2 through xxxIP0, allow the default priority level of 4.
interrupt to be assigned to one of eight relative priority
levels. The other difference is the number of interrupt
sources. While many interrupts have the same (or very
Disabling User Interrupts
similar) name as PIC18F devices, others are new. Other To disable interrupts on PIC18F devices, it is only
interrupts have similar names but have a different mean- necessary to clear the GIE bit (GIEH or GIEL if priority
ing from their PIC18F counterparts. Users should refer to levels are used).
the appropriate PIC24F device data sheet for a complete
To disable user interrupts on PIC24F devices, these
list of interrupts and their meanings.
steps are required:

Setup and Enabling Interrupts 1. Push the current STATUS Register (SR) value
onto the software stack using the PUSH instruction.
The following are the required steps to set up and 2. Force the CPU to Priority Level 7 by inclusive
enable interrupts on PIC18F devices: ORing the value, 0Eh, with the low byte of the
1. Clear the interrupt flag status bit associated with STATUS Register. To enable user interrupts, the
the peripheral in the associated PIRx or POP instruction may be used to restore the
INTCONx register. previous STATUS Register value.
2. Enable the interrupt source by setting the interrupt Note: The DISI instruction allows interrupts of
enable control bit associated with the source in Priority Levels 1-6 to be disabled for a
the appropriate PIEx or INTCONx register. fixed period of time.
Note: The interrupt flag still needs to be cleared
prior to exiting an ISR. Migration Considerations
Optional steps: PIC18F architecture only has the ability to assign either
high or low-priority interrupts to individual sources.
1. Select the user-assigned priority level for the
PIC24F architecture allows the assignment of multiple
interrupt source by writing to the control bits in
priority levels for interrupts (Priorities 0 through 7 are
the RCON register. Select high priority or low
user-defined and Priorities 8 through 15 are hardware-
priority using the priority bit in the corresponding
defined). At the very least, interrupts in native PIC18F
IPRx register. The interrupt priority feature is
applications will need to be reassessed and their
enabled by setting the IPEN bit (RCON[7]).
priority levels redefined in PIC24F terms.
2. (On newer PIC18F devices) Enable or disable the
Interrupt Vector Table using the MVECEN Config- For both PIC18F and PIC24F devices, the RETFIE
uration bit and configure the IVTBASE register for instruction exits an Interrupt Service Routine (ISR), but
the location of the Interrupt Vector Table. this instruction does behave slightly different depend-
ing on the microcontroller. For PIC18F, this instruction
The following are the required steps to set up and will set the GIE bit to re-enable global interrupts. Since
enable interrupts on PIC24F devices: the GIE bit does not exist for PIC24F, this instruction
1. Set the NSTDIS bit (INTCON1[15]) if nested will restore the previous priority level.
interrupts are not desired.
2. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
3. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
Note: The Interrupt/trap flag still needs to be
cleared prior to exiting an ISR.

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SERIAL PERIPHERAL INTERFACE The PIC24F SPI peripheral is considered a “stand-alone”
peripheral, where PIC18F devices incorporate the SPI
(SPI)
function into the larger Master Synchronous Serial Port
The PIC24F SPI peripheral is a superset of the PIC18F (MSSP) peripheral, which also includes I2C. But PIC18F
architecture and many of the features are similar. devices with DMA have a similar stand-alone SPI module
PIC18F devices with DMA have many more features as in the PIC24F family.
closer to the PIC24F SPI features. The differences
between the SPI peripherals of PIC18F and PIC24F
devices are presented in Table 5.

TABLE 5: SPI FEATURE COMPARISON

PIC18F
Features PIC24F
with MSSP with Stand-Alone SPI
Master and Slave Mode Yes Yes Yes
Clock Polarity and Edge Select Yes Yes Yes
FIFO No Yes Yes
Separate Transmit and Receive Buffer No Yes Yes (Enhanced mode)
Dedicated Baud Rate Counter No Yes Yes
Operation with DMA No Yes Yes(2)
Transfer Data Width 8 1 to 8-bit 8/16
Frame Mode Support No No Yes
Peripheral Pin Select (PPS) No Yes Yes(1)
I2S No No Yes(2)
Note 1: Not all devices have PPS, refer to the device-specific data sheet to check for the PPS feature availability.
2: I2S is available only on PIC24F variants, such as PIC24FJ128GA310, PIC24FJ128GB204,
PIC24FJ256GB410/412 and PIC24FJ1024GA/GB610. Check the specific device data sheet for feature
availability.

Migration Considerations Differences Between PIC18F Devices

The only significant issue when migrating is the Master
without DMA and PIC18F Devices with DMA
mode clock frequency calculation. Because the PIC24F Like the PIC24F devices, PIC18F devices with DMA
instruction clock is based on FOSC/2, the peripheral have distinct SPI and I2C modules, instead of a shared
clock is at a different rate than the PIC18F architecture. MSSP module. This SPI also has several features,
Use the equations in the “Serial Peripheral Interface such as FIFOs and separate transmit/receive buffers,
(SPI)” chapter of the specific device data sheet to that make migration from the PIC18F devices with DMA
calculate the correct SPI clock speed. to PIC24F devices even more straightforward.

 2019 Microchip Technology Inc. DS00002991A-page 7

INTER-INTEGRATED CIRCUIT (I2C)
Both PIC18F and PIC24F architectures support 7 and
10-Bit Addressing modes, General Call Addressing,
clock stretching, 100 and 400 kHz data rates and multi-
master networking. Table 6 shows comparisons of the
features available in PIC24F and PIC18F devices.

TABLE 6: I2C FEATURE COMPARISON

PIC18F
Features PIC24F
with MSSP with Stand-Alone I2C
Supported Bus Speeds 100 kHz/400 kHz 100 kHz/400 kHz/1 MHz 100 kHz/400 kHz/1 MHz
10-Bit Addressing Mode No Yes Yes
Multi-Master Support Yes Yes Yes
Configurable Address Masking 6 Bits 7 or 10 Bits 7 or 10 Bits
General Call Support No Yes Yes
Clock Stretching Option Yes Yes Yes
Operation with DMA No Yes No
Slew Rate Control Yes Yes Yes
I2C/SMBus Input Levels Yes Yes Yes
Reserved Address Support Yes(1) Yes Yes
Bus Repeater Mode No No Yes
Firmware Mode Yes No No(2)
Note 1: Refer to the specific device data sheet for information on which addresses are reserved for particular devices.
2: The PIC24F I2C peripheral does not have a Firmware Controlled Master mode configuration (similar to the
PIC18F mode, where SSPM[3:0] = 1011). As a result, PIC24F I2C firmware implementation must use port
input (VIH and VIL) levels.

Migration Considerations Differences Between PIC18F Devices

Differences between the PIC24F and PIC18F I2C
without DMA and PIC18F Devices with DMA
peripherals can lead to some complications during Like the PIC24F devices, PIC18F devices with DMA
migration. A common issue is to not account for the have distinct SPI and I2C modules, instead of a shared
address shift in the I2CxMSK and I2CxADD registers. MSSP module. This I2C also has several features,
The Least Significant I2C address bit in the PIC18F such as 10-Bit Addressing and general call support,
SSPxADD register is bit ‘1’, where in the PIC24F that make migration from PIC18F devices with DMA to
I2CxADD register, it is bit ‘0’. A simple shift prior to PIC24F devices even more straightforward. The stand-
loading or after reading the address will resolve the alone PIC18F I2C module also has SMBus 3.0 input
difference. level support.

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DIRECT MEMORY ACCESS (DMA) without intervention from the CPU. By eliminating the
need for CPU-intensive management of handling inter-
PIC24F devices, as well as some of the PIC18F rupts intended for data transfers, the CPU can now
devices, support the DMA feature. The Direct Memory spend more time on other tasks. The differences
Access (DMA) module is designed to service data between the DMA of PIC18F and PIC24F devices are
transfers between different memory regions directly, presented in Table 7.

TABLE 7: DMA FEATURE COMPARISON

PIC18F
Features PIC24F(1)
PIC18F without DMA PIC18F with DMA
DMA No Yes Yes
Multiple DMA Channel Support No Yes Yes
Transfer mode No Yes Yes
(data memory to SFR/SFR to data memory)
Data Read from EEPROM/Flash No Yes No
Addressable Source and Destination No Yes Yes
Start Using Software Trigger No Yes Yes
Start Using Interrupt Trigger No Yes Yes
Source Address Increment/Decrement Mode No Yes Yes
Destination Address Increment/Decrement Mode No Yes Yes
Separate Counter for Source and Destination No Yes No
DMA Abort Interrupt Trigger No Yes No
Note 1: DMA is available only on PIC24F variants, such as PIC24FJ128GA310, PIC24FJ128GB204,
PIC24FJ256GB410/412 and PIC24FJ1024GA/GB610. Check the specific device data sheet for feature
availability.

Migration Considerations Differences Between PIC18F Devices

without DMA and PIC18F Devices with DMA
There are some differences in the features of the DMA,
as well as the mode of operation, between the PIC18F The DMA is one of the defining features of newer
and PIC24F families. some of the major differences are PIC18F devices.
explained below:
1. One of the major differences in the DMA
between the PIC18F and PIC24F families is the
ability for a PIC18F device to access the Flash
program memory and the data EEPROM
memory for read operation. In PIC24F devices,
the data can only be transferred between SFRs
and data RAM or vice versa. In PIC18F devices,
the SMT[1:0] (DMAxSSA) bits can be used to
point to where the source data can be read from.
SMTx bits can point to the data read from SFRs/
GPRs, EEPROM or program Flash.
2. Another difference is the count or the size of the
data to be communicated. In PIC24F devices,
there is only one count or size register, whereas
in PIC18F devices, there is a size register for
both destination (DMAxDSZ) and source
(DMAxSSZ) registers.

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LIQUID CRYSTAL DISPLAY (LCD) and PIC24F devices. The LCD functionality on the
devices is very similar and it is easy to migrate from a
PIC24F devices, as well as some of the PIC18F PIC18F device to a PIC24F device. Some of the
devices support the LCD module. The following is the features, operation and comparisons of the LCD
comparison of the LCD features between the PIC18F module are shown in Table 8.

TABLE 8: LCD FEATURE COMPARISON

Features PIC18F(1) PIC24F(1)
LCD Yes Yes
LCD Operation in Sleep Yes Yes
Static, 1/2 and 1/3 Bias Yes Yes
(2)
4 COM and 8 COM Multiplexing Yes Yes
Charge Pump Biasing(3) Yes Yes
External Resistor Biasing Yes Yes
Internal Resistor Ladder Biasing(4) Yes Yes
Type A and Type B Support Yes Yes
LCD Prescaler Option Yes Yes
Multiple Option for LCD Clock Yes Yes
Note 1: Not all devices support LCD. Check the specific device data sheet to make sure the LCD is supported.
2: Multiplexing of 8 COM is not supported on all LCD devices. Make sure to check the specific device
data sheet to see if 8 COM is supported.
3: The charge pump is supported for LCD operation when the VDD is going below the LCD glass specifica-
tion. Not all devices support this feature. Please refer to the device data sheet to check the availability of
the specific features supported.
4: An internal resistor is provided to generate the bias voltage needed for the LCD module internally; this is to
save board space and cost. There is dynamic resistor switching implemented based on the user need to
keep the current consumption low. Verify with the device data sheet for more details; all the LCD devices
may not have the feature implemented.

Migration Considerations Differences Between PIC18F Devices

The features and mode of operation of the LCD is very
without DMA and PIC18F Devices with DMA
similar in PIC18F and PIC24F devices. The only care There is no current PIC18F device with DMA that
that needs to be taken is if the system clock is used as supports the LCD peripheral.
the LCD clock. Depending on the specific device clock,
the prescaler clock for the LCD should be corrected so
that the LCD is within an acceptable range of operation.

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UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER (UART)
PIC24F devices, as well as some of the PIC18F
devices support the UART module. Table 9 shows the
comparison of the UART features between the PIC18F
and PIC24F devices.

TABLE 9: UART FEATURE COMPARISON

PIC18F(1)
Features PIC18F without PIC24F(1)
PIC18F with DMA
DMA
Asynchronous (full-duplex) Operation with: Yes Yes Yes
• Auto-Wake-up on Character Reception
• Auto-Baud Calibration
• 12-Bit Break Character Transmission
Full-Duplex 8 or 9-Bit Data Transmission through Yes Yes Yes
the TX and RX Pins
Support for 9-Bit Mode with Address Detect Yes Yes Yes
(9th bit = 1)
Hardware Flow Control Option with UxCTS and No Yes Yes
UxRTS Pins
Number of Stop Bits 1 1, 1.5, 2 1, 2
Selectable Idle Polarity No Yes Yes
Baud Rate Generator Dedicated 8-Bit/16-Bit Dedicated 8-Bit/16-Bit 16-Bit
BRG Prescaler Yes Yes Yes
IrDA® Encoder and Decoder Logic No No Yes
16x Baud Clock Output for IrDA Support No No Yes
FIFO Transmit Data Buffer No Yes Yes
FIFO Receive Data Buffer No Yes Yes
Loopback Mode for Diagnostic Support No No Yes
Hardware Parity Support (8-bit data) No No Yes
Parity Error Detection No Yes Yes
Hardware Sync Byte Generation Yes Yes Yes
Support for Sync and Break Characters Yes Yes Yes
Wake-up Enable Yes Yes Yes
Framing and Buffer Overrun Error Detection Yes Yes Yes
Interrupt Options Transmit and Transmit, Receive and Transmit, Receive and
Receive UART Error Event UART Error Event
DMX No Yes Yes
DALI No Yes Yes
LIN No Yes Yes
Note 1: Not all devices may include these features. Please refer to the device data sheet to check the availability
of the specific features supported.

Note: The PIC24F UART does not support synchronous communications. If synchronous serial communication
is required, use the SPI module instead.

 2019 Microchip Technology Inc. DS00002991A-page 11

Migration Considerations Differences Between PIC18F Devices
When migrating from a PIC18F design to a PIC24F, the
without DMA and PIC18F Devices with DMA
following must be taking into consideration: PIC18F devices with DMA add hardware protocol sup-
1. Because the fundamental instruction cycle rate is port (DMX, DALI and LIN/J2602), as well as several
different (FOSC/2 for PIC24F, FOSC/4 for PIC18F), other features that make migration to PIC24F devices
projects that are being ported from PIC18F to more straightforward. In addition, like the PIC24F
PIC24F will need to have baud rates recalculated. UART, they do not support the Synchronous mode that
2. Routines for 9-bit communication will need to be older PIC18F devices do.
modified. PIC18F USARTs require the 9th bit to
be read from, or written to, another register.

DS00002991A-page 12  2019 Microchip Technology Inc.

REAL-TIME CLOCK AND CALENDAR Table 10 shows the key features and differences of the
Real-Time Clock and Calendar (RTCC) between the
(RTCC)
PIC18F and PIC24F devices.
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.

TABLE 10: RTCC FEATURE COMPARISON

Features PIC18F(1) PIC24F(1)
RTCC(1) Yes Yes
Updates Time: Hours, Minutes and Seconds Yes Yes
24-Hour Format (military time) Yes Yes
Calendar: Weekday, Date, Month and Year Yes Yes
Configurable Alarm Yes Yes
Year Range: 2000 to 2099 Yes Yes
Leap Year Correction Yes Yes
BCD Format for Compact Firmware Yes Yes
Low-Power Operation Yes Yes
User Calibration Yes Yes
External 50 Hz or 60 Hz External Input No Yes
User Calibration Effect in Seconds Every 60 Seconds Every 15 Seconds
Alarm Repeat Yes, Up to 255 Times Yes, Up to 255 Times
Alarm Mask Yes Yes
RTCC Power Control No Yes
Selectable Clock Source Yes Yes
Note 1: Not all PIC24F and PIC18F devices support the RTCC module. Please refer to the specific device data
sheet to check if the RTCC module is available. Some of the PIC18F devices with RTCC include the
PIC18F46J11, PIC18F46J50,PIC18F87J94, PIC18F87J90, PIC18FX7J13 and PIC18F87J72 families.
Some of the PIC24F devices with RTCC include the PIC24FJ128GA010, PIC24FJ128GA310,
PIC24FJ128GB410, PIC24FJ128GB204, PIC24FJ256GA610, PIC24FJ64GA006, PIC24FJ32MC104 and
PIC24FJ256GA705 families.

Migration Considerations Differences Between PIC18F Devices

When migrating from a PIC18F design to a PIC24F, the
without DMA and PIC18F Devices with DMA
following must be taken into consideration: There is no current PIC18F device with DMA that
1. The features for the RTCC module are very similar supports the RTCC peripheral.
between the devices, but the PIC24F devices
include some additional features. For the legacy
RTCC attributes, there are no major differences.
For the RTCC input clock options, please verify
with the specific device data sheet.

 2019 Microchip Technology Inc. DS00002991A-page 13

CYCLIC REDUNDANCY CHECK (CRC) Legacy PIC18F devices do not have hardware CRC
support, but PIC18F devices with DMA have a similar
GENERATOR
CRC module to the PIC24F devices. The differences
The PIC24F CRC module allows for hardware calcula- between the CRC modules are outlined in Table 11.
tions of CRC checksums, instead of having to utilize
software bandwidth to complete the same calculations.

TABLE 11: CRC FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Polynomial Size N/A Up to 16 Up to 16
Interrupt N/A Upon CRC Completion as well as On CRC Completion
Scanner Completion
NVM Scanner N/A Scans Program Memory or No
EEPROM and Feeds Data to
CRC Engine
Input FIFO N/A No 8-Deep, 16-Bit or 16-Deep, 8-Bit

Migration Considerations Differences Between PIC18F Devices

The primary consideration when migrating from PIC18F
without DMA and PIC18F Devices with DMA
is that the PIC18F CRC module is primarily used with the Only PIC18F devices with DMA support this module.
NVM scanner to perform CRC checksums on program
memory. The PIC24F CRC module does not contain a
built-in scanner the way the PIC18F module does, so it
will require the use of software or other modules to per-
form the same functionality. In addition, the PIC24F CRC
module has a FIFO on its input instead of just a single
set of registers, so inputting data to the module works
slightly differently.

DS00002991A-page 14  2019 Microchip Technology Inc.

TIMERS signal measurement timer, a 32-bit timer meant for per-
forming capture/compare and measuring functions on
PIC24F timers broadly support the basic PIC18F timer incoming digital signals, both of which have specific
features found in Timer0 and Timer1/3/5, including functions. Conversely, each PIC24F 16-bit timer has a
Asynchronous and Synchronous Counter modes, Timer dedicated period register, selectable prescaler and
and Gated Timer modes, and 32 kHz crystal support. period match flag, and can operate in either Counter or
PIC24F timers are designed to have more generic func- Timer mode for generic purposes. Two 16-bit PIC24F
tions, whereas PIC18F timers are intended for dedicated timers can also be combined to make a single 32-bit
purposes. This specialization has only increased with timer. The differences between the Timer module of
PIC18F devices with DMA, which include the new 8-bit PIC18F and PIC24F devices are presented in Table 12.
Timer2/4/6 module with hardware limit functions and the

TABLE 12: TIMERS FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Timer Width 8/16-Bit 8/16/24-Bit 16/32-bit
General Purpose Timer Mode All Timers All Timers All Timers
Asynchronous Counter Mode Timer1/3 All Timers Timer1/2/4
Synchronous Counter Mode Timer0/1/3 All Timers All Timers
Period Register Timer2/4 Timer0/2/4/6 and SMT All Timers
32 kHz Crystal Support Timer1 All Timers Timer1
Other Clock Sources No All Timers No
Timer Gate Option No Timer1/3/5 All Timers
Prescaler All Timers All Timers All Timers
Postscaler Timer2/4 Timer0/2/4/6 No
Special Event Trigger Yes Yes Yes
System Clock Source Rate FOSC/4 FOSC/4 FOSC/2
Hardware Limit Features No Timer2/4/6 No
Signal Measurement Features (pulse No SMT No
width, time between edges)

Migration Considerations PIC18F devices with DMA to PIC24F devices has even
fewer considerations, as most features are shared
The biggest consideration of migration is that timer between the two.
functionality may not be on the same timers between
PIC18F and PIC24F devices. Period registers are on all The newer PIC18F devices also have some new timers
PIC24F timers, rather than only some of the PIC18F for more specific applications. The Timer2/4/6 module on
timers. Prescalers are present on both architectures, but PIC18F devices with DMA is an 8-bit timer with a period
PIC18F prescalers differ by each timer, while PIC24F register, which can be started, run, frozen or reset by
prescalers are the same for each timer. Finally, PIC24F external signals (either from other peripherals or an exter-
timers do not have postscalers, a feature that is common nal pin). The module also has One-Shot and Monostable
on many PIC18F timers. Either a software solution or modes. These timers can be used with the PWM to
different prescaler/period option may be needed in order perform more sophisticated waveform control, such as
to achieve the same timer period on a PIC24F device. pulse density modulation. There are no equivalent timers
on the PIC24F devices.
Differences Between PIC18F Devices PIC18F devices with DMA also have the SMT, a 24-bit
without DMA and PIC18F Devices with DMA timer intended for measuring a variety of digital signal
parameters (such as pulse width, frequency and duty
The PIC18F devices with DMA have many more timer cycle), as well as use as a synchronous timer or asyn-
features than the legacy variants, which make them chronous counter. It also has gated timer features and
match up better with PIC24F devices and make migra- a period match register. There is no equivalent timer on
tion easier. Both Asynchronous and Synchronous the PIC24F devices, although the 32-bit timers on the
modes are now available on all timers, along with 32 kHz PIC24F can perform most of the non-signal measure-
crystal support. More timers have period registers, and ment functions of the SMT (for example, if the SMT is
Timer1, 3 and 5 offer gated timer functionality. These only being used as a large timer).
features mean that migrating generic timer code from

 2019 Microchip Technology Inc. DS00002991A-page 15

CONFIGURABLE LOGIC CELL (CLC) feature, but PIC18F devices with DMA also have a CLC
module. The CLC modules between the PIC18F
The PIC24F CLC module allows the user to specify devices with DMA and PIC24F devices are almost
combinations of signals as inputs to a logic function identical. Table 13 below shows the differences in the
and to use the logic output to control other peripherals CLC modules.
or I/O pins. Legacy PIC18F devices have no equivalent

TABLE 13: CLC FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Number of Input Selections (total) 0 Up to 64 Up to 32
Number of Input Selections 0 Up to 64 Up to 8
(per data gate)
Logic Output to Other Peripherals N/A Yes Yes
CLC Output Pin N/A Relocatable with PPS Fixed Pin
Interrupt N/A Rising and Falling Edges Rising and Falling Edges
Output Enable N/A Controlled through PPS Separate Control Bit

Migration Considerations Differences Between PIC18F Devices

The only considerations when migrating from PIC18F
without DMA and PIC18F Devices with DMA
CLCs to PIC24F CLCs is with the inputs and outputs. Only PIC18F devices with DMA support this module.
The PIC24F CLCs are more limited in their CLC inputs.
The PIC18F CLC modules allow for up to 64 inputs and
allow those inputs to go to all four of the data gates,
while the PIC24F devices have only 32 inputs, of which
only eight go to each data gate. In addition, both the
input and output pins for the PIC18F CLC can be
moved through PPS, while the CLC pins on PIC24F
devices are static. Finally, due to the output pins’ static
nature, the PIC24F CLC has a separate output enable
pin that needs to be considered when outputting the
CLC to said external pin.

DS00002991A-page 16  2019 Microchip Technology Inc.

CAPTURE/COMPARE/PWM
(CCP AND ECCP)
The PIC24F capture and compare modules exhibit the
same features as the PIC18F CCP and ECCP
peripherals. The differences between the CCP periph-
erals of PIC18F and PIC24F devices are presented in
Table 14.

TABLE 14: CCP/ECCP FEATURE COMPARISON

Features PIC18F(1) PIC24F(1)
CCP/ECCP Features Yes Yes
Configurable Timer Sources Yes Yes
Capture Pin Prescaler 1, 4, 16 1, 4, 16
Capture Buffer Yes Yes
Capture Timer Width Yes Yes
Selectable Captures per Interrupt Yes Yes
Selectable Output Compare Pin States Yes Yes
Special Event Trigger Yes Yes
Number of PWM Outputs per Peripheral Yes Yes
Half-Bridge/Full-Bridge PWM Support Yes Yes
PWM Dead-Band Support No(2) Yes
Note 1: Please refer to the device data sheet to check the availability of the specific features supported.
2: Devices with CWG (Configurable Waveform Generator) and COG (Configurable Output Generator) offer
dead-band support. Check the device data sheet to see if the feature is supported.

The PIC24F input capture and output compare modules input clock features for these devices. Please refer to
can use either Timer2 or Timer3, where the PIC18F the device data sheet to check the availability of the
modules can use either Timer1 or Timer3. Capture events MCCP or SCCP modules.
can be generated on every rising, falling, 4th rising and
16th rising edge of the ICx pin. Migration Considerations
With Single Compare Match mode selected, both archi-
The PIC24F output compare peripheral clock source is
tectures can select the initial state of the OCx pin. Upon
based on FOSC/2 which differs from the PIC18F FOSC/4
the match, the pin can either transition or toggle. For
clock source. Ensure the equations available in the
each mode and in both architectures, the output
product data sheet are used for the various clock
compare interrupt flag is set.
source calculations.
All of the PIC18F PWM modes are supported by the
PIC24F family. The significant difference is that each Differences Between PIC18F Devices
output compare peripheral can generate only one
without DMA and PIC18F Devices with DMA
output. Therefore, half-bridge support requires two
peripherals and full-bridge support requires four. The primary difference in the CCP module between
PIC24F PWM mode is an extension of the output legacy PIC18F variants and PIC18F devices with DMA
compare peripheral. This mode is similar to the Single is not directly related to the CCP, but instead, to the
Output Compare mode and with the addition of Fault timers. Both the Timer1 and Timer2 have differences in
protection pins, OCFA and OCFB, can stop the pulse them from legacy variants that may affect how the CCP
train; similar to the PIC18F PWM mode. operates, which should be taken into consideration.
PIC18F devices with DMA also have the Compli-
Some of the PIC24F devices have dedicated modules, mentary Waveform Generator (CWG) module which
called MCCP and SCCP, which stands for the Multiple supports PWM with dead band.
or Single Capture/Compare peripheral. The devices
that include these modules have multiple modes of
operation, where they can work as a timer, capture,
compare, as well as a PWM option. There are multiple

 2019 Microchip Technology Inc. DS00002991A-page 17

I/O PORTS
PIC24F I/O ports are very similar to the PIC18F ports,
but have noteworthy differences. Both families of
devices have data PORT, LAT and TRIS registers. Both
device families have analog and digital peripherals.
The differences between the I/O ports of PIC18F and
PIC24F devices are presented in Table 15.

TABLE 15: I/O PORTS FEATURE COMPARISON

PIC18F(1)
Features PIC24F(1)
PIC18F without DMA PIC18F with DMA
Control Registers: PORTx, LATx Yes Yes Yes
and TRISx
Internal Pull-up Only on PORTB On All Ports On All Ports
Configured to Inputs on Reset Yes Yes Yes
Open-Drain Control No Yes Yes
PPS Yes(1) Yes Yes
Interrupt-on-Change Selective Pins Yes Yes
Note 1: Not all devices will have this feature. Please refer to the device data sheet to check the availability of the
specific features supported.

Unsupported PIC18F Features • Most of the input buffers for PIC24F devices are
Schmitt Triggers (ST). Verify that the output levels
The PIC24F port architecture does not permit the port of associated components meet the ST input
output to drive the peripheral input. The user must voltage thresholds.
either configure the pin as a peripheral input or port
• Making the pins analog or digital can vary from
output, but not both.
device to device. Some of the PIC18F devices
have this control in the ADC registers. Some of
Migration Considerations the PIC24F devices have a register, called
• Enabling a digital or analog input or output onto a ADxPCFG, to implement the same feature. Some
pin with a configurable open-drain option will not of the PIC18F and PIC24F devices have
cause the pull-up to be automatically disabled. dedicated registers for each pad to make the pins
The pull-up is not disabled if the pin has a configu- analog or digital (ANSELx register).
rable open-drain option. It is important to disable
the pull-up in software when it is not needed. Differences Between PIC18F Devices
• Pins without an analog function can tolerate input without DMA and PIC18F Devices with DMA
voltages up to 5.5V. This can minimize hardware
There are few to no differences between PIC18F
changes when migrating from a PIC18F device. A
devices with DMA and PIC18F devices without DMA in
higher voltage output can be created by adding an
respect to I/O port controls.
external pull-up resistor on the pin and writing a
zero to the data latch. Setting the TRISx bit will
pull the output up to the supply voltage and
clearing the TRISx bit will output a digital zero.
• Drive strength, slew rate and input voltage thresh-
olds can change automatically when a peripheral
is enabled. It is important to review the specific
data sheets for differences between devices.

DS00002991A-page 18  2019 Microchip Technology Inc.

OSCILLATOR features to enhance application robustness, such as
software-controlled clock switching, Fail-Safe Clock
The PIC24F oscillator system supports many of the Monitors (FSCM) and Two-Speed Start-up. PIC24F
features of the PIC18F and adds several new features. devices increase the flexibility of initial clock configura-
Both architectures support three major clock sources: tion, software-controlled clock switching and the use of
primary oscillators, internal RC oscillators and 4x PLL the PLL. The differences between the oscillator of
frequency multipliers. In addition, both also support PIC18F and PIC24F devices are presented in Table 16.

TABLE 16: OSCILLATOR FEATURE COMPARISON

PIC18F(1)
Features PIC24F(1)
PIC18F without DMA PIC18F with DMA
Primary (external) Oscillator Modes HS, XT, EC, LP and HS, XT, LP and EC HS, XT and EC
External RC(2) (all devices)
Secondary (Timer1) Oscillator Yes Yes Yes
8 MHz Internal RC Oscillator Yes (INTOSC) Yes (HFINTOSC) Yes (FRC)
32 kHz Internal RC Oscillator Yes (INTRC) Yes (MFINTOSC/ Yes (LPRC)
LFINTOSC)
4x PLL Options:
• XTPLL (MSPLL) No No Yes
• ECPLL Select Devices Only Yes Yes
• INTOSCPLL/FRCPLL Select Devices Only No Yes
Software Clock Switching Between Clock Sources Yes Yes
Only(1)
Doze Mode No Yes Yes
Fail-Safe Clock Monitor Yes(1) Yes Yes
(1)
Two-Speed Start-up Yes Yes Yes
Note 1: Not all devices will have this feature. Please refer to the device data sheet to check the availability of the
specific features supported.
2: Not all PIC18F devices have an External RC oscillator, refer to the specific device data sheet.

Primary Oscillators (POSC) Internal RC Oscillators (INTOSC/FRC and

In PIC18F devices, the exact oscillator mode to be
INTRC/LPRC)
used is selected during device configuration using the Both PIC24F and PIC18F families feature two indepen-
FOSC[3:0] Configuration bits. In some of the newer dent internal oscillators, an efficient 31 kHz oscillator and
PIC18F devices, the POSC mode is selected by an accurate, high-speed 8 MHz oscillator. Some of the
FEXTOSC[2:0] and the actual boot up oscillator is newer devices have a selectable frequency, from 1 MHz
selected by RSTOSC[2:0]. In PIC24F devices, the to 64 MHz. Both architectures use a configurable
Primary Oscillator mode is selected during configuration postscaler, driven by the 8 MHz source, to provide a
with a combination of the FNOSC[2:0] and POSCMD[1:0] range of clock frequencies, from 31 kHz to 4 MHz (as well
Configuration bits. as the undivided 8 MHz output). Both architectures allow
software selection from the 31 kHz or 8 MHz oscillators
Secondary Oscillator (SOSC) to provide the 31 kHz source for various system features.
All PIC18F devices have the option to use the Timer1 PIC18F and PIC24F devices both support a 4x PLL
oscillator as a secondary clock source. The most frequency multiplier for use with select clock sources.
typical arrangement for this option is to connect a low- In all cases, the PLL provides a stable output only when
power, 32 kHz watch crystal across pins, T1OSI and the input frequency is between 4 and 10 MHz. For a
T1OSO. The oscillator is controlled separately from the detailed description of the PLL operation, please refer
device clock by the T1OSCEN bit (T1CON[3]). to the device data sheet.
PIC24F devices also provide a Secondary Oscillator
that is identical in function to the Timer1 oscillator; it
only differs in that it is controlled through the OSCCON
register with the SOSCEN bit. The crystal input/output
pins are renamed SOSCI and SOSCO.

 2019 Microchip Technology Inc. DS00002991A-page 19

Two-Speed Start-up For PIC24F devices, any one of the three major clock
sources can be configured as the default start-up oscil-
Two-Speed Start-up is implemented identically in lator; users are no longer confined to just the primary
PIC18F and PIC24F devices. In both cases, the feature oscillator sources. During run time, the device can
is controlled by the IESO Configuration bit. Some of the switch between any of the available oscillator modes
new PIC18F devices will not have the Two-Speed under software control. This means that, among other
Start-up feature; please check the device data sheet for things, it is possible to switch between a Primary Clock
details. mode and its PLL. PIC24F devices unlock the high or
low byte for one instruction after two specific literals are
Fail-Safe Clock Monitor written to the high or low byte of OSCCON. Please refer
to the compiler manual and device data sheet for the
The Fail-Safe Clock Monitor feature is also available for
specifics of writing to OSCCON and clock switching.
both the device families. It is controlled, along with run-
time clock switching, by the Configuration Word bits.
Implementation is very similar in both PIC18F and Migration Considerations
PIC24F devices, where the system clock automatically When migrating to a PIC24F microcontroller (or any
switches to the FRC when the primary oscillator stops. microcontroller, for that matter), any application that is
based on a crystal clock source should be re-evaluated
Clock Switching for oscillator operation and stability. It is important to
verify that the crystal performance is reliable across the
Clock switching differs significantly between PIC18F
voltage, temperature and process variations anticipated
and PIC24F devices. Conceptually, both architectures
for the application.
have three categories of oscillators: primary (external
components connected to OSC pins), secondary
(external crystal connected to T1OSC or SOSC pins) Differences Between PIC18F Devices
and internal RC. without DMA and PIC18F Devices with DMA
PIC18F devices permit the definition of one and only Conceptually, there are few differences in oscillators
one primary oscillator type used during device configu- between PIC18F devices with DMA and PIC18F devices
ration. This is the oscillator that is always used when on without DMA; there are only a few minor setup/Configu-
device power-up and Reset. Thereafter, the device can ration register changes.
switch between primary, secondary and internal
oscillator sources under software control. In the newer
PIC18F family devices, the RSTOSC configures which
oscillator is used at start-up and the FEXTOSC selects
the oscillator type.
Once a start-up oscillator is defined, it cannot be
changed unless the device is reprogrammed.

DS00002991A-page 20  2019 Microchip Technology Inc.

POWER-SAVING FEATURES Run-Time Clock Switching
PIC24F power-saving features are very similar to the PIC18F and PIC24F devices have all the same types of
power-saving modes offered in PIC18F XLP Technology system clock sources (Primary, Secondary and Internal
devices. Both architectures include run-time switching of Oscillator). In addition, Sleep and Idle modes are
system clock sources, Idle and Sleep modes, and hard- defined in the same manner. The process of how the
ware invoked exits through Resets and interrupts. clock switching is achieved is different between PIC18F
PIC24F devices describe these features in a somewhat and PIC24F families; please check the device data
different manner and support additional features for sheet for the steps to be followed for clock switching.
strategic reduction of power consumption. The differ-
ences between the power-saving features of PIC18F
and PIC24F devices are presented in Table 17.

TABLE 17: POWER-SAVING FEATURE COMPARISON

PIC18F(1)
Features PIC24F(1)
PIC18F without DMA PIC18F with DMA
Run-Time Clock Switching Yes Yes Yes
Idle Mode Yes Yes Yes
Selective Peripheral Idle No No Yes
Sleep Mode Yes Yes Yes
(1)
Low-Voltage Sleep (Retention Sleep) Yes Yes Yes(1)
Deep Sleep Yes(1) No Yes(1)
Doze Mode No Yes Yes
PMD Option No Yes Yes
Note 1: Not all devices will have this feature. Please refer to the device data sheet to check the availability of the
specific features supported.

 2019 Microchip Technology Inc. DS00002991A-page 21

RESETS • Stack Error Reset (Overflow or Underflow)
PIC24F devices have some additional Reset sources/
The PIC24F Reset system shares most of its features
states, along with some enhanced reporting. The Reset
with the PIC18F Reset system. The same legacy
states for SFRs and start-up timing from Resets also
Resets are supported in either identical or functionally
differs slightly. In addition, PIC18F devices with DMA
equivalent methods:
have Reset system enhancements that differ from the
• Power-on Reset (POR) ones made in PIC24F. The major differences are
• Brown-out Reset (BOR) shown in Table 18.
• External Master Clear Reset (MCLR)
• Software Reset (RESET instruction)
• Watchdog Timer (WDT) Reset

TABLE 18: RESETS FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA

Legacy Reset Types POR, BOR, MCLR, RESET Instruction

Additional Reset Types Configuration Word Memory Violation, Watchdog Illegal Opcode/Uninitialized W,
Mismatch (PIC18FXXJ Timer Window Violation Configuration Word Mismatch,
Flash devices) Trap Conflict
BOR Configuration Configurable, Configurable, Tied to On-Chip Regulator(1)
Software-Controllable in Software-Controllable in
Many Devices Many Devices
Stack Underflow/Overflow Reset Separate Resets Unmaskable Trap
Reset
SFR Reset States Dependent on Type of Dependent on Type of Reset Uniform for All Reset Types
Reset
Start-up Timer Configurable Configurable Tied to Regulator
Configuration
Flag Bits Location RCON/STKPTR PCON0/1 RCON/INTCON1
Note 1: Some of the devices include the feature to enable or disable BOR; please refer to the device data sheet to
check the availability of the BOR feature.

Migration Considerations often necessary to read all of the Reset flags to deter-
mine the cause of the Reset, while on the PIC24F
All legacy PIC18F Resets are also supported by devices, often only one flag needs to be read).
PIC24F devices (in addition to a few additional Reset
sources). The primary migration concern is in how the
Differences Between PIC18F Devices
PIC24F handles stack overflow/underflow cases. While
these cases trigger a Reset on PIC18F devices, they without DMA and PIC18F Devices with DMA
are instead implemented as traps in the PIC24F PIC18F devices with DMA have two additional Reset
architecture. In theory, this leads to more flexibility in sources not on legacy PIC18F devices without DMA.
handling stack overflow/underflow instances, but appli- The first is a Watchdog Timer Window Violation Reset,
cations that expect a Reset on stack overflow will need which is covered in the “Watchdog Timer” section of
to take this change into account. A secondary migration this document. The second is the Memory Execution
concern is that PIC24F devices do not have a configu- Violation Reset, which occurs if the core attempts to
rable start-up timer, so the timer will need to be execute code from either an address outside
accounted for instead of programmed. The third major implemented program memory or from the specially
consideration is that the polling of Resets is different designated storage area Flash. PIC24F devices do not
between PIC18F devices and PIC24F devices, with have equivalents to either of these Resets. Other than
PIC24F Reset flags being active-high instead of these two additional sources, Resets on PIC18F
PIC18F active-low bits, and the PIC24F Reset bits devices with DMA behave the same as PIC18F devices
being more narrowly defined (on PIC18F devices, it is without DMA.

DS00002991A-page 22  2019 Microchip Technology Inc.

A/D CONVERTER (ADC)
The PIC24F ADC has significant improvements in
performance and features over the PIC18F implemen-
tation (see Table 19). Improvements include higher
conversion rate (samples per second), Automatic
Channel Scan mode, 16-bit conversion result buffer, etc.

TABLE 19: A/D CONVERTER FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Resolution 10/12-Bit 12-Bit 10/12-Bit
Conversion Throughput (ksps) 100 ksps — 500 ksps
Available Voltage Reference Sources Internal/External Internal/External Internal/External
Selectable A/D Clock Divider Yes Yes Yes
A/D RC Oscillator Yes Yes Yes
Auto-Sample Yes Yes Yes
Programmable Sample Time Yes Yes Yes
Individually Selectable Analog Inputs No Yes Yes
Special Event Trigger No Yes Yes
Multiple Channel Scan No Yes Yes
FIFO Buffer No Yes, 2-Level Yes
Multiple Result Formats No Yes Yes
Differential Channel (comparative) No No Yes
Conversion

The PIC24F and PIC18F A/D Converter modules have • When configuring the A/D to use the conversion
similar features. Both have a 10-bit, Successive clock, several factors will affect the PIC24F
Approximation Register (SAR) A/D, capable of using a divider selection. These include the reduced TAD
combination of reference pins (VREF+ and VREF-) and and the instruction rate. The PIC24F conversion
analog power pins (AVDD and AVSS) for the reference clock is based on the instruction clock, TCY/2,
voltages. Both product lines feature an A/D conversion where the PIC18F is based on FOSC/2. Due to
status bit, selectable A/D clock divider, dedicated A/D different instruction rates for a given system clock
RC, auto-sampling with configurable sample time, frequency, the smallest period for the PIC24F A/D
analog/digital input selection and run-time selectable clock divider is one FOSC period and two FOSC
A/D input. Conversions can be initiated by software, an periods for PIC18F.
external interrupt or an output compare event.
Differences Between PIC18F Devices
Migration Considerations without DMA and PIC18F Devices with DMA
• The source impedance for the PIC24F module is PIC18F devices with DMA add a few additional features
2.5 kOhm. Many PIC18F devices are 10 kOhm, to the PIC18F ADC module. First, there are hardware
although 2.5 kOhm is recommended. CVD controls, which allow for better use of the ADC
• For the PIC24F module, the module’s internal module for capacitive touch applications. Second,
sampling capacitor is 4.4 pF, typical; for the there is a hardware calculation engine (ADC features)
PIC18F module, it is 25 pF, typical. The reduced that allows for core-independent hardware averaging
capacitance increases the affect of the external and low-pass filtering of ADC results.
capacitance on the analog input.

 2019 Microchip Technology Inc. DS00002991A-page 23

WATCHDOG TIMER bits and software) and affects (WDT can also be a
Reset to be used to exit power-managed modes). The
The Watchdog Timer (WDT) module for the PIC24F is PIC24F WDT has a few unique features, as well as
nearly identical to both the WDT on PIC18F devices some features missing from the legacy PIC18F
without DMA and the WDT on PIC18F devices with devices, but added on PIC18F devices with DMA. The
DMA. All have similar controls (both in Configuration comparison of the modules is shown in Table 20.

TABLE 20: WATCHDOG TIMER FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Configurable Time-out Period Yes (through postscaler) Yes (through prescaler) Yes (through prescaler
and postscaler)
Software Enable Yes Yes Yes
Exit Power-Managed Modes Yes Yes Yes
Time-out Range 4 ms to 131s 1 ms to 256s 1 ms to 131s
Windowed WDT Option No Yes Yes
Selectable Input Clock No Yes No

Migration Considerations Differences Between PIC18F Devices

The first migration consideration is that the PIC24F WDT
without DMA and PIC18F Devices with DMA
counter resets on any clock source switch of the main PIC18F devices with DMA have additional features on
clock. The PIC18F WDT counter resets on a variety of the WDT, as well as some slight differences in setup.
conditions, which are outlined in the “Watchdog Timer The primary setup difference is that the period is con-
(WDT)” section of the data sheet for the PIC18F device figured using a prescaler instead of a postscaler, and
in question. The second consideration is that the WDT the prescaler allows for 1 ms to 256s periods, scaling
Reset flag in PIC18F devices is active-low, while the one logarithmically (1 ms, 2 ms, 4 ms, up to 256s). This
on PIC24F devices is active-high, and these bits will means that a 131s period is not possible on PIC18F
need to be initialized to the inactive state at POR or BOR devices with DMA. In addition, PIC18F devices with
to properly detect WDT Resets. When migrating a legacy DMA have Windowed Watchdog Timer features, much
PIC18F device, ensure to use the 1:128 prescaler setting like the PIC24F devices, which makes the two Watch-
on the PIC24F device to allow for the same postscaler dog Timers even more similar between PIC18F
settings to be used between the two devices. When devices with DMA and PIC24F families.
migrating a PIC18F device with DMA, the period must
be manually calculated using the prescaler/postscaler
on the PIC24F device to match the one on the PIC18F
device. In addition, when migrating a Windowed
Watchdog Timer application from a PIC18F device with
DMA to PIC24F devices, bear in mind that the PIC24F
window is non-programmable and fixed at a
75% window delay (window setting, ‘0b001’, on PIC18F
Windowed Watchdog Timers).

DS00002991A-page 24  2019 Microchip Technology Inc.

COMPARATOR AND COMPARATOR configuration selections. The PIC18F version has only
eight selections, one of which is disabling comparators.
VOLTAGE REFERENCE MODULES
The PIC24F version is more configurable, allowing
The comparator modules on the PIC18F and PIC24F individual control over many of the options that are
devices share many of the same features. Table 21 fixed on PIC18F. In addition to the comparator module,
shows the feature comparison of PIC18F and PIC24F both PIC18F and PIC24F offer a comparator voltage
devices. Each has two comparators with various reference based on a resistor ladder circuit.

TABLE 21: COMPARATOR FEATURE COMPARISON

PIC18F(1)
Features PIC24F(1)
PIC18F without DMA PIC18F with DMA
Comparators 2 2 2/3
Output Inversion Control Yes Yes Yes
(2)
Separate Comparator Enables Yes Yes Yes
Comparator Output on I/O Pin Yes Yes Yes
Multiple Input Selections Yes Yes Yes
Detecting Individual Comparator Tracked in Firmware by User Hardware Hardware
Output Changed States
Note 1: Please refer to the device data sheet to check the availability of the specific features supported.
2: Some of the PIC18FJ family devices have a comparator similar to PIC24F devices, please refer to the
specific device data sheet for more details.

Migration Considerations Some of the PIC18FJ devices have the comparator

control bits implemented similar to the PIC24F devices,
PIC18F devices with DMA have more options as where each comparator has its own dedicated
compared to older PIC18F devices without DMA. They Comparator Control register instead of controlling both
have more input options, as well as the interrupt to be comparators from one Comparator Control register.
generated on the positive or negative comparator Please refer to the device data sheet for specifics on
output transitions. The devices also have dedicated the implementation of these control bits.
register selection for the inverting and non-inverting
inputs of the comparator. The status of the output pin is
also mirrored in the register as a read-only status bit.
This is different in the internal CVREF option as there
are no CVREF pins used. Alternatively, a dedicated
DAC output can be used to connect to the input pins.

 2019 Microchip Technology Inc. DS00002991A-page 25

Comparator Voltage Reference Module
The comparator voltage reference module is used along
with the comparator to provide internally controlled volt-
age reference to the comparator input. This helps the
user to control the reference voltage using software. The
module is compatible between the PIC24F and PIC18F
family devices. Table 22 shows the feature comparison of
PIC18F and PIC24F devices.

TABLE 22: COMPARATOR VOLTAGE REFERENCE FEATURE COMPARISON

PIC18F
Features PIC24F
PIC18F without DMA PIC18F with DMA
Resistor Ladder 16-Tap N/A(1) 16-Tap
Two Selectable Ranges Yes N/A(1) Yes
Selectable Reference from Ana- Yes N/A(1) Yes
log Power or MCU Power
Voltage Reference Output Yes N/A(1) Yes
Enable
Note 1: In the PIC18F devices with DMA, the CVREF module is not used; the devices have a dedicated 5-bit DAC
to provide reference to the comparator input.

DS00002991A-page 26  2019 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision A (March 2019)

This is the initial version of this document.

 2019 Microchip Technology Inc. DS00002991A-page 27

NOTES:

DS00002991A-page 28  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in
headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries.
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
CERTIFIED BY DNV ISBN: 978-1-5224-4285-1

== ISO/TS 16949 ==

 2019 Microchip Technology Inc. DS00002991A-page 29

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DS00002991A-page 30  2019 Microchip Technology Inc.

08/15/18