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IAT-3 - Question Bank AVLSI

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14 views1 page

IAT-3 - Question Bank AVLSI

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bhc21ec
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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USN

CMR INSTITUTE OF TECHNOLOGY

AVLSI- IAT 3 Question Bank

Module 4

1. Explain the purpose of void functions in System Verilog.


2. Write a simple task in SystemVerilog to toggle an LED every 5 time units.
3. Analyze the impact of incorrect time value usage in procedural statements.
4. Evaluate the efficiency of using tasks versus functions in a complex test bench.
5. Design a SystemVerilog routine that calculates the factorial of a given number using tasks or
functions.
6. Illustrate the role of SystemVerilog assertions in validating a design.
7. Write a simple interface in SystemVerilog to connect a 4-bit counter design with its test bench.
8. Design a complete test bench using SystemVerilog that includes an interface construct, stimulus
timing, and assertions for a simple ALU module.
Module 5

1. Explain the purpose of randomization in verification environments.


2. Write a SystemVerilog example to randomize the values of a 3-bit register within the range
1–6.
3. Analyze the behavior of a pseudo-random number generator versus a truly random number
generator.
4. Design a constrained randomization scenario where a packet's header fields must follow specific
protocol rules.
5. Write a SystemVerilog example to define and trigger a cover group for monitoring bus
transactions.
6. Evaluate the effectiveness of generic cover groups in improving reusability across verification
projects.
7. Create a strategy to analyze and measure coverage statistics to identify gaps in a testbench.
8. Compare and contrast data sampling methods for cover groups.

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