University of Technology Digital Electronics Laboratory

Department of Electrical and Electronic Engineering Third Year

EXPERIMENT NUMBER (3)

ASYNCHRONOUS AND SYNCHRONOUS COUNTERS

OBJECT

After completing this experiment you will be able to:

1- Build and analyze various asynchronous and synchronous up and

down counters.
2- Change the modulus of the counter.
3- Use an IC counter and determine how the truncate its count sequence.

THEORY

A digital counter is a logic circuit that can progress through a

sequence of numbers or status when activated number contained within
the counter at any given time. Counters are classified into two board
categories according to the way they are clocked asynchronous and
synchronous.

1- Asynchronous counter

In asynchronous counters, commonly called ripple counters, the

flip- flop is clocked by the external clock plus and then each successive
flip-flop is clocked by the output of the proceeding flip flop. Figure (3-1)
shows a two- bit counter connected for asynchronous operation, notice
that the clock (CLK) is applied to the clock input (C) of only the first flip-
flop (FF0). The second flip flop (FF1) is triggered by the Q0 output of
FF0. FF0 changes state of the positive-going edge of each clock plus, but
FF1 changes only when triggered by a positive-going transition of the Q0
output of FF0. Figure (3-2) shows the timing diagram of the Q0 and Q1
outputs.

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Department of Electrical and Electronic Engineering Third Year

Fig. (3-1) Two bit asynchronous binary counter.

Fig. (3-2) Timing diagram for the counter of Fig. (3-1).

A three bit asynchronous binary counter is shown in Figure (3-3a).

The basic operation is the same as that of the two bit counter just
discussed; except that the three counters has eight states, due to its three
flip- flops. A timing diagram shown in Figure (3-3b) progresses though a
binary counter of zero through seven and then recycles to the zero state.
This counter sequence is listed in Table (3-1).

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University of Technology Digital Electronics Laboratory
Department of Electrical and Electronic Engineering Third Year

Table (3-1) Binary state sequence for a 3- bit binary counter.

Clock Pulse Q2 Q1 Q0

Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8(Recycle) Repeat

( a)

(b)
Fig. (3 -3) Three bit asynchronous binary counter and its timing
diagram for one cycle.

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University of Technology Digital Electronics Laboratory
Department of Electrical and Electronic Engineering Third Year

2- Asynchronous Decade Counter

The most common modulus for counters with truncated sequence is

ten (called MOD 10). Counters with ten states in their sequence are called
decade counters. A decade counter with a count sequence of zero (0000)
through nine (1001) is a BCD decade counter because its ten- state
sequence produces the BCD code. Let's use a 4-bit asynchronous counter
such as the one in Figure (3-4) and modify its sequence to illustrate the
principle of turn coded counters. This decade counter sequence listed in
Table (3-2).

Table (3-2) Binary state sequence for an Asynchronous Decade Counter.

Clock Q3 Q2 Q1 Q0

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

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Department of Electrical and Electronic Engineering Third Year

Fig. (3- 4) An asynchronous clocked decade counter.

3- Synchronous Counter

In this case, the clock input is connected to all of the flip- flops so
that they are clocked simultaneously. Within each of these two
categories, counters are classified primarily by the type of sequence, the
number of states, or the number of flip- flops in the counter. The
synchronous counters also called a parallel counter. Figure (3- 5) shows a
2-bit synchronous binary counter. Notice that arrangement different from
that for the asynchronous counter must be used for the J1 and K1 inputs
of FF1 in order to achieve a binary sequence. Figure (3 -6) shows the
timing diagram of the Q0 and Q1 outputs.

Fig. (3 -5) A 2-bit synchronous binary counter.

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Fig. (3 -6) Timing diagram for the counter of Fig. (3-5).

Figure (3 -7) shows a 4-bit synchronous binary counter this circuit

can be connected by using IC 74136 which has several features in
addition to basic function previously discussed for the general
synchronous binary counter. First the counter can be preset to any four-
bit binary number by applying the proper levels to the data inputs. When
a low is applied to the load input the counter will assume the state of the
date inputs on the next clock pulse. This allows the counter sequence to
be with any four- bit binary number. Also there is an active low clear
input which reset all four flip-flops in the counter. There are two enable
inputs, P and T these inputs must be high for the counter to sequence
through its binary state. When at least one is low, the counter is disabled.
The carry, output goes HIGH when the counter reaches the last state in
the sequence, binary 1s.

Data In

CLK

Q3 Q2 Q1 Q0

Fig. (3 -7) 4-bit synchronous binary counter.

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4- Synchronous Decade Counters

Decade counters are very important category of digital counters

because of their wide application. A decade counter has ten states in its
sequence that is, it has a modulus often. It consists of four stages and can
have any given sequence of states as long as there are ten. A very
common type of decade counter is the BCD (8421) counter. As you can
see the BCD decade counter goes through a straight binary sequence
through the binary 9 state. Rather than going to the binary 10 state, it
recycle to the 0 state. Synchronous BCD decade counter is shown in
Figure (3 -8).

Fig. (3-8) Synchronous BCD decade counter.

APPARATUS

1- OSCILLOSCOPE
2- OSCILLATOR
3- LOGIC INTIKIT UNIT
4- IC's: 7404, 7408, 7432, 74190, 74163, 7472, 7493, 7490.

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PROCEDURE

Part one: Implementation using practical connection.

1- Connect the circuit shown in Figure (3-1) and find the truth
table and its timing diagram using IC (7472).
2- Connect the circuit shown in Figure (3-3a) and find its truth
table and timing diagram using IC (7472).
3- Design four stage asynchronous counter by using IC (7493) to
and find its truth table and timing diagram.
4- Connect the circuit shown in Figure (3-4) and find the truth
table and its timing diagram.
5- Repeat step (4) using IC (7490).
6- Connect the circuit shown in Figure (3-5) and find the truth
table and its timing diagram using IC (7472).
7- Connect the circuit shown in Figure (3-7) and find the truth
table and its timing diagram.
8- Repeat step (7) using IC (74163).
9- Design the BCD/ UP-DOWN counter by using IC (74190), and
find its truth table and timing diagram for BCD Down counter.
Part two: Computer Simulation using (EWB).
1. Connect the circuit shown in Figure (3-1) and find its truth
table and timing diagram using IC (7472) and seven segment
display.
2. Connect the circuit shown in Figure (3-3a) and find its truth
table and timing diagram using IC (7472) and seven segment
display.
3. Design four stage synchronous counter by using IC (7493) to
and find its truth table and timing diagram.

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4. Repeat step 1, 2 and 3 using blocks.

5. Connect the circuit shown in Figure (3-4) and find its truth
table and timing diagram using IC (7490).
6. Connect the circuit shown in Figure (3-5) and find the truth
table and its timing diagram using IC (7472) and seven
segment display.
7. Connect the circuit shown in Figure (3-7) and find the truth
table and its timing diagram using IC (7472) and seven
segment display.
8. Repeat step 6 and 7 using blocks.
9. Connect the circuit shown in Figure (3-7) using IC 74136.
10. Design the BCD/ UP-DOWN counter by using IC (74190)
and find its truth table and timing diagram for BCD Down
counter.

DISCUSSION

1- The state diagram for a positive edge- triggered counter

shown in Figure (3-9), sketches the corresponding timing
diagram.

CK1 CK2 CK3 CK4 CK5

start 0 1 3 5 7 9

0000 0001 0011 0101 0111 1001

Fig. (3-9)

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Department of Electrical and Electronic Engineering Third Year

2- Given a BCD decade counter, show the decoding logic

required to decode each of the following state and how it
should be connected to the counter. A HIGH output
indication is required for each decoded state. MSB is to the
left. (a) 0110 (b) 0111 (c) 1000

3- Determine the sequence of the counter shown in Fig. (3-10).

SA QA SB QB SC QC

ck ck ck

RA QA RB QB RC QC

Clock

Fig. ( 3-10)
4-Design a counter that count the following sequence: 2, 4, 5, 8, 12
and repeat using J-K FLIP- FLOP.
5-For the circuit shown, draw the timing diagram and its truth
table, assume initially zero for each flip- flop.
1 1

JA QA JB QB JC QC

Clock ck ck ck

KA QA KB QB KC QC

1
Fig. (3-11)
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