Unit-6

Unit-6
DIGITAL
DIGITAL ELECTRONICS
ELECTRONICS
 1’s Complement Subtraction, If M>N
Subtract (1010)2 from (1111)2

Direct Subtraction 1’s Complement Method

1 1 1 1 15 1 1 1 1
- 1 0 1 0 -10 1’s complement of 1010 ➡ + 0 1 0 1
result ➡ 1 0 1 0 0
0 1 0 1 5 Add Carry ➡ 1
Final result ➡ 0 1 0 1

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 1’s Complement Subtraction, If M<N
Subtract (1111)2 from (1010)2

Direct Subtraction 1’s Complement Method

1 0 1 0 10 1 0 1 0
- 1 1 1 1 -15 1’s complement of 1111 ➡ + 0 0 0 0
result ➡ 1 0 1 0
- 0 1 0 1 -5 No Carry is generated, the result in 1’s
complement form
1’s comp of 1010➡ -0 1 0 1

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 2’s Complement Subtraction, If M>N
Subtract (1010)2 from (1111)2

Direct Subtraction 2’s Complement Method

1 1 1 1 15 1 1 1 1
- 1 0 1 0 -10 2’s complement of 1010 ➡ + 0 1 1 0
result ➡ 1 0 1 0 1
0 1 0 1 5 Ignore Carry ➡
Final result ➡ 0 1 0 1

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 2’s Complement Subtraction, If M<N
Subtract (1111)2 from (1010)2

Direct Subtraction 2’s Complement Method

1 0 1 0 10 1 0 1 0
- 1 1 1 1 -15 2’s complement of 1111 ➡ + 0 0 0 1
result ➡ 1 0 1 1
- 0 1 0 1 -5 No Carry is generated, the result in 2’s
complement form
2’s comp of 1011➡ -0 1 0 1

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Logic Gates
Logic gate is an electronic circuit, which makes logical
decisions. It has two or more inputs and only one output except for
the NOT gate, which has only one input. The output appears only for
certain combinations of the input signals.

Truth Table: The relationship between input and output variables of

each gate can be represented in a tabular form is called a Truth
table.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Classification of Logic Gates

BASIC UNIVERSAL EXCLUSIVE

GATES GATES GATES

NOT NAND XOR

AND NOR XNOR

0R
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 AND gate Input Input Output
A B AB
0 0 0

0 1 0

1 0 0
The output of AND gate is low, if
any one input is low or all the 1 1 1

inputs are low and is high if all the

inputs are high.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 OR gate
Input Input Output
A B A+B

0 0 0
0 1 1
The output of an OR gate is high if any
1 0 1
one input is high or all inputs are high
1 1 1
and is low if all the inputs are low.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 NOT gate
Input A Output A’

0 1

The output is the complement of the input. 1 0

When the input is High then the output is
‘Low’. When the input Low then the
output is High.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Universal Gates or Universal Building
Blocks
• NAND and NOR gates are called universal gates
because both the gates can be used to
implement any other gates like AND, OR, NOT
or any combination of these basic gates.
NAND: The output of NAND gate is high if any one
input is low or all inputs are low and is low if all inputs
are high.
NOR: The output of NOR gate is low if any one input
is high or all inputs are high and is high if all the
inputs are low.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Universal Logic Gate (NAND)
A A
Z = Z
B B

Z = (A . B) Z = A + B

Input Input Output

A B AB

0 0 1

0 1 1

1 0 1

1 1 0

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Universal Logic Gates (NOR)
A A
Z = Z
B B

Z = (A + B) Z = A . B

Input Input Output

A B A+B

0 0 1

0 1 0

1 0 0

1 1 0

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Exclusive OR (EX-OR) or XOR
XOR Input Input Output
A B A⊕B
A 0 0 0
Z 0 1 1
B
1 0 1
Z = A ⊕ B 1 1 0

The output of an EX-OR gate is high for odd number of

1’s and is low for even number of 1’s.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

Exclusive NOR (EX-NOR) or XNOR Gates
Input Input Output
XNOR A B A⦿B
A 0 0 1
Z
B 0 1 0
1 0 0
Z = A ⦿ B 1 1 1

The output of an EX-OR gate is Low for odd number of

1’s and is High for even number of 1’s.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

AND, OR, NOT Operations using NAND Gate

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AND, OR, NOT Operations using NOR Gate

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Codes
The different binary codes can be classified as:
Weighted codes
Non Weighted codes
Reflective codes
Sequential codes
Error Detecting and Correcting codes
In weighted codes each digit position is assigned with
certain weight.
Examples: 8421, 2421
In un-weighted codes each digit position is not assigned
with certain weight.
Examples: Gray code, Excess – 3 code.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 4 Bit BCD Codes
➢ Coding schemes are used to store decimal numbers.
➢ Examples: BCD (or 8421), 2421, etc.
Decim
➢ Each decimal digit is represented as a 4-bit al digit
BCD
binary code.
0 0000
1 0001
Binary Code Decimal (BCD)
2 0010
8 – 4 – 2 – 1 CODE 3 0011
INDICATES THE WEIGHT OF EACH BIT 4 0100
23 – 22 – 21 – 20
5 0101
Eg: 934 = 1001 0011 0100 6 0110
7 0111
9 3 4 8 1000
9 1001

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 2421 Code
• The 2421 code is called as self complementing or reflective code
and it is a weighted code. In this the bit 1 & bit 3 have same
weight (2), bit 2 has the weight (4) and bit 0 has the weight (1).
Decimal digit 2421
0 0000
1 0001
2 0010
3 0011
4 0100
5 1011
6 1100
7 1101
8 1110
9 1111
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Excess-3 or Ex-3 or XS-3 code
• It is a modified form of a BCD number. The ex-3
code can be derived from the natural BCD code by
adding 3 to each coded number. Decimal
digits
Excess-3
code
Ex: 15 in BCD is 0001 0101 0 0011

15 in XS-3 is 0100 1000 1 0100

2 0101
• It is also called as: 3 0110
-Sequential code 4 0111
5 1000
-Self complementing or 6 1001
Reflective Code 7 1010
8 1011
9 1100
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Gray Code or Unit Distance Code or
Cyclic Code
• The code, which exhibits only a single bit
change from one code number to the next
code number. In other words, each gray code
number differs from the preceding number by
a single bit.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Binary to Gray Code Conversion
Binary Code: 1 0 0 1 1 0 1 1 A B XOR
0 0 0
0 1 1
Gray Code: 1 1 0 1 0 1 1 0 1 0 1
1 1 0

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Binary to Gray Code Conversion

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Gray to Binary Code Conversion
Gray Code: 1 0 0 1 1 0 1 1 A B XOR
0 0 0
0 1 1
Binary Code: 1 1 1 0 1 1 0 1 1 0 1
1 1 0

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Decimal Gray Binary
Number Code Code
0 0000 0000
1 0001 0001
2 0011 0010
3 0010 0011
4 0110 0100
5 0111 0101
6 0101 0110
7 0100 0111
8 1100 1000
9 1101 1001
10 1111 1010
11 1110 1011
12 1010 1100
13 1011 1101
14 1001 1110
15 1000 1111
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Reflective or Self Complementing
Codes
• A code is said to be reflective or self
complementing code, When the code for 9 is the
complement for 0, the code for 8 is the
complement for 1, 7 for 2, 6 for 3 and 5 for 4.
These codes are used to perform 9’s complement
subtraction.
• Ex: 2421, Excess-3
• A weighted code is said to be self complementing
code, if the sum of all weights equal to 9.
• Ex: 2421

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Reflective Property of 2421 Code
Decimal Complement Decimal
Relation

0000
0 1111 9

0001
1 1110 8

0010
2 1101 7

0011
3 1100 6

0100
4 1011 5

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Sequential Code
• In sequential code, each succeeding code is
one binary number greater than its preceding
code.
• Ex: 8421, XS-3 codes

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 What is Error?
Error is a condition when the output information does
not match with the input information. During
transmission, digital signals suffer from noise that can
introduce errors in the binary bits travelling from one
system to other. That means a 0 bit may change to 1 or a
1 bit may change to 0 as shown in Figure1.

Figure 1:Error Occurred due to the Noise

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Error Detection and Error Correction Code
➢ Error Detecting Codes : The codes, which are used to
detecting the errors in a communication system.

➢ Types of Error detection

❖ Parity Code
❖ Hamming Code

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 What is Parity
A parity bit, or check bit is an extra bit included
with a binary message to make the number of 1’s either
even or odd.
Even
Parity bit
Odd
• Even parity -- Even parity means the number of 1's in
the given word including the parity bit should be even
(2,4,6,....).
• Odd parity -- Odd parity means the number of 1's in
the given word including the parity bit should be odd
(1,3,5,....).
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Error Detection

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

➢ Error Correcting Codes : The codes, which are used
to detecting and correcting the errors in a
communication system.
➢ Hamming Code:
• Hamming code not only provides the detection of a bit
error, but also identifies which bit is in error so that it
can be corrected. Thus, the hamming code is called an
error detecting and error correcting code. It is used to
detect & correct a single bit error and also used to
detect a double bit error.
• The code uses a number of parity bits, depending on the
number of information bits located at certain positions
in the code group.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Number of Parity Bits Required for Hamming Code
• If the number of information bits is designed ‘X’ then the
number of parity bits ‘P’ is determined by the following
relationship
2P ≥ X+P+1
• For example, if we have 5 information bits, that is X=5 then
P is found by trial and error using equation.
Let P=2 22 ≥ 5+2+1
4 ≥ 8 (Not satisfied)
Let P=3 23 ≥ 5+3+1
8 ≥ 9 (Not satisfied)
Let P=4 24≥ 5+4+1
16 ≥ 10 (Satisfied)
• Therefore 4-parity bits are required to transmit 5 information
bits. Therefore total code consists of 9-bits.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Location of Parity Bits in the Code
• The parity bits are located in the positions that
are numbered corresponding to ascending
powers of 2 i.e 1, 2, 4, 8,16 etc.
• For 9-bit code, the locations for parity bits and
information bits are shown below:

D5 P4 D4 D3 D2 P3 D1 P2 P1
9 8 7 6 5 4 3 2 1

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Bit Position Table for Hamming Code
Bit D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit location 9 8 7 6 5 4 3 2 1
Binary
location
1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Information
bits (Dn)
Parity bits
(Pn)

Calculation of parity bits:

P1 checks the bit locations ( 3, 5, 7, 9, 11...)
P2 checks the bit locations ( 3, 6, 7, 10,11..)
P4 checks the bit locations ( 5, 6, 7,12....)
P8 checks the bit locations ( 9, 10, 11, 12...)
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 Encoder Operations
• Prob: Encode the binary word 1110110 into even parity hamming
code.

Number of information bits, X = 7

Step 1: Find the number of parity bits required:
2P ≥ X+P+1
Let P=2; 22 ≥ 7+2+1
4 ≥ 10 (Not satisfied)
Let P=3; 23 ≥ 7+3+1
8 ≥ 11 (Not satisfied)
Let P=4; 24≥ 7+4+1
16 ≥ 12 (Satisfied)
• Therefore, 4 parity bits are required to transmit 7 information bits and the
parity bits are placed in the powers of 2 i.e 1,2,4,8 bit locations.
• Total Code = Information bits + Parity bits = 7 + 4 = 11 Bits.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
Step 2 : Draw the bit location table
Bit D7 D6 D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit location 11 10 9 8 7 6 5 4 3 2 1
Binary
location
1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Information 1 1 1 0 1 1 0
bits (Dn)
Parity bits P4 P3 P2 P1
(Pn)

Step 3: Parity bits calculation:

For P1: The bit locations 3, 5, 7, 9, 11 have three-1’s or odd number of 1’s.
Therefore P1 = 1.
For P2: The bit locations 3, 6, 7, 10, 11 have three-1’s or odd number of 1’s.
Therefore P2 = 1.
For P3: The bit locations 5, 6, 7 have two-1’s or even number of 1’s.
Therefore P3 = 0.
For P4: The bit locations 9, 10, 11 have three-1’s or odd number of 1’s.
Therefore P4 = 1.
Bit D7 D6 D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit location 11 10 9 8 7 6 5 4 3 2 1
Binary
location
1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Information 1 1 1 0 1 1 0
bits (Dn)
Parity bits 1 0 1 1
(Pn)

Final Encoded Hamming Code is: 11110110011

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Decoder Operations
Check for Parity Bits: The detection and correction algorithm
P1 checks the bit locations (1,3, 5, 7, 9, 11)-LSB works on the following ‘3’ conditions.
P2 checks the bit locations ( 2,3, 6,7, 10,11) 1. If C=0 and P5=0
P3 checks the bit locations (4, 5, 6, 7)
P4 checks the bit locations ( 8,9, 10, 11)-MSB There is no error in the transmitted
codeword, so the codeword is taken as
Binary Word Formed: C = P4 P3 P2 P1 valid information.

2. If C ≠ 0 and P5= 1
P5 checks the bit locations from 1 to 11
A single bit error occurred that can be
detected and corrected.

3. If C ≠ 0 and P5= 0

Double bit error occurred that cannot

be corrected, so the codeword is taken
as invalid information.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 (i) No Error Condition (C=0, P5=0)
Prob: The hamming code 11110110011 is received. Correct it if any errors with
even parity.
Bit D7 D6 D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit Location 11 10 9 8 7 6 5 4 3 2 1
Binary 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Location No
Received 1 1 1 1 0 1 1 0 0 1 1
Code
• Check for Parity Bits:
• P1 checks the bit locations (1,3, 5, 7, 9, 11) has four number of 1’s. Therefore
for even parity P1 = 0 (LSB).
• P2 checks the bit locations ( 2,3, 6,7, 10,11) has four number of 1’s.
Therefore for even parity P2=0.
• P3 checks the bit locations (4, 5, 6, 7) has two number of 1’s. Therefore for
even parity P3=0.
• P4 checks the bit locations ( 8,9, 10, 11) has four number of 1’s. Therefore
for even parity . P4=0 (MSB)
 From the above, P4 = P3=P2=P1 =0
• The Binary Word Formed:
C = P4 P3 P2 P1 = 0000
Hence C=0
• P5 checks the bit locations from (1 to 11) has even number of
1’s. Therefore overall parity P5 =0.
Finally C=0, P5=0
So, it is clear that there is no error in the transmitted codeword.
So the codeword is taken as a valid code.

Finally decoded hamming code is: 11110110011

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 (ii) Single Error Condition(C≠0, P5=1)
Prob: The hamming code 11111110011 is received. Correct it if any
errors with even parity.
Bit D7 D6 D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit Location 11 10 9 8 7 6 5 4 3 2 1
Binary 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Location No
Received 1 1 1 1 1 1 1 0 0 1 1
Code

• Check for Parity Bits:

• P1 checks the bit locations (1,3, 5, 7, 9, 11) has five number of 1’s. Therefore
for even parity P1 = 1 (LSB).
• P2 checks the bit locations ( 2,3, 6,7, 10,11) has five number of 1’s. Therefore
for even parity P2=1.
• P3 checks the bit locations (4, 5, 6, 7) has three number of 1’s. Therefore for
even parity P3=1.
• P4 checks the bit locations ( 8,9, 10, 11) has four number of 1’s. Therefore for
even parity . P4=0 (MSB)
 From the above, P4 = 0, P3=1, P2=1, P1 =1
• The Binary Word Formed:
C = P4 P3 P2 P1 = 0111
Hence C=0 and it shows that error occurred in 7th (0111) bit
position.
• P5 checks the bit locations from (1 to 11) has 9 number of 1’s.
Therefore for even parity , overall parity P5 =1.
Finally C=0, P5=1
• So, it is clear that a single bit error occurred that can be detected
and corrected. so the codeword is taken as valid information.
• So, we can easily correct the error by inverting the 7th bit
position. i.e. 1 as 0.
• Final Decoded Hamming code is:
11110110011
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 (iii) Double Error Condition (C≠0, P5=0)
Prob: The hamming code 01110110111 is received. Correct it if any
errors with even parity.
Bit D7 D6 D5 P4 D4 D3 D2 P3 D1 P2 P1
designation
Bit Location 11 10 9 8 7 6 5 4 3 2 1
Binary 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Location No
Received 0 1 1 1 0 1 1 0 1 1 1
Code
• Check for Parity Bits:
• P1 checks the bit locations (1,3, 5, 7, 9, 11) has four number of 1’s. Therefore
for even parity P1 = 0 (LSB).
• P2 checks the bit locations ( 2,3, 6,7, 10,11) has four number of 1’s.
Therefore for even parity P2=0.
• P3 checks the bit locations (4, 5, 6, 7) has two number of 1’s. Therefore for
even parity P3=0.
• P4 checks the bit locations ( 8,9, 10, 11) has three number of 1’s. Therefore
for even parity . P4=1 (MSB)
 From the above, P4 = 1, P3=0, P2=0, P1 =0
• The Binary Word Formed:
C = P4 P3 P2 P1 = 1000
Hence C=0
• P5 checks the bit locations from (1 to 11) has 8 number of 1’s.
Therefore for even parity, overall parity P5 =0.
Finally C=0, P5=0
• So, it is clear that Double bit error occurred that cannot be
corrected, so the codeword is taken as invalid information.

Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC

 Problems on Hamming Code
• Encode the binary word 0110101 into odd parity
hamming code.

• The hamming code 001100101110 is received. Correct

it if any errors with odd parity.

• The hamming code 111011001001 is received. Correct

it if any errors with odd parity.

• The hamming code 001110110111 is received. Correct

it if any errors with odd parity.
Basic Electronics Engineering Unit-II Ms. M. DIVYA Dept of ECE, REC
 BOOLEAN ALGEBRA
Fundamental Postulates of Boolean Algebra
SOP & POS
Minterms & Maxterms
Combinational Logic Circuit:

Adder:
Adder is used to add the bits of information.
Half-Adder:
A combinational logic circuit that performs the addition of two data bits A and B is called half adder. Addition
will result in two output bits; one of which is the sum bit S, and the other is the carry bit Cout. The Boolean
functions describing the half adder are:
𝑆=𝐴 𝐵
𝐶out = 𝐴.B
Logic Symbol:

Truth Table:
Inputs Outputs
A B S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logic Diagram:
Full Adder:
The half-adder does not take the carry bit from its previous stage into account. The carry bit from its previous
stage is called carry-in bit, Cin. A combinational logic circuit that adds two data bits A and B, and a carry-in
bit Cin is called a full-adder. Addition in this adder will result in two output bits; one of which is the sum S,
and the other is the carry out Cout. The Boolean functions describing for full-adder are:

𝑆=𝐴 𝐵 𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝐴.𝐵 + 𝐵.𝐶𝑖𝑛 + 𝐴.𝐶𝑖𝑛
or
𝐶𝑜𝑢𝑡 = (𝐴 𝐵).𝐶𝑖𝑛 + 𝐴.B
Logic Symbol:

Truth Table:
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic Diagram:

Block Diagram:
Full Adder using two Half Adders:
Register: A group of flip flops can bre used to store a
word is called Register. A flip flop can store 1-bit of
information. so an n-bit register has a group of n-flip flops
and is capable of storing any binary information contain-
ing n-bits.