Parul University
Parul University
PARUL UNIVERSITY
FACULTY OF ENGINEERING & TECHNOLOGY
BTech, winter 2023-24
Semester: 3 Date: 24/01/2024
Subject Code: 303105220 Times: 10:30 am to 1:00 pm
Subject Name: Digital Electronics Total Marks: 60
Instructions:
1. All questions are compulsory.
2. Figures to the right indicate full marks.
3. Make suitable assumptions wherever necessary.
4. Start new question on new page.
Q.1 Objective Type Questions - ( Fill in the blanks, one word answer, MCQ-not more (15) CO PO BT
than Five in case of MCQ) (All are compulsory) (Each of one mark)
1. TTL Stand for________ 1 2 R
2. Full form of SOP ________ & POS _____________. 1 2 R
3. In adder A=1, B=1 and C=0; so what is the value of Sum and carry? 2 1 U
4. Which of the following gives the correct number of multiplexers required to build a 2 2 U
32 x 1 multiplexer?
A. Two 16 x 1 mux B. Three 8 x 1 mux C. Two 8 x 1 mux D. Three 16 x 1
mux
5. PLAs, CPLDs, and FPGAs are all which type of device? 1 2 R
A.SLD B.PLD C.EPROM D.SRAM
6. How many bits are needed to store one BCD digit? 2 1 U
A. 2 bits B. 4 bits C. 3 bits D. 1 bit
7. What will be the output from a D flip-flop if D = 1 and the clock is low? 2 1 U
A. No change B. Toggle between 0 and 1 C. 0 D. 1
8. FPGA stands for ________ 1 2 R
9. On which condition J-K flip-flop made to toggle? 2 1 U
A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1
10. The 9's complement of 6578 is________. 2 1 U
11. What is the addition of the binary number 101001+ 010011=? 2 1 U
A. 010100 B. 111100 C. 000111 D.101110
12. CPLD stands for ________________. 1 2 R
13. Convert binary number into gray code: 100101. 3 3 A
14. Write a Duality theorem. 1 2 R
15. Normally synchronous inputs are PRESET and CLEAR. (True/False) 1 2 R
Q.4 A) Explain D flip flop in detail and explain difference between latch and flip-flop. (07) 3 4 A
OR
A) Explain R-2R Ladder DAC with circuit diagram. (07) 4 5 E
B) Explain 8*1 using 4*1 multiplexer. With truth table and circuit diagram. (08) 5 6 C
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