A Technical discussion on
Advanced PLL Design Techniques for High-Performance Signal
Processing
ATAL FDP on Next-Gen System-on-Chip Design for Advanced Semiconductor Solutions
On August 13 2024
At
RV College of Engineering
By
Nithin Muralidharan
Outline
✓ Basic Introduction to the need of phase locking
✓ Role of PLL in wireline applications
✓ Introduction to Jitter
✓ Jitter calculations – how to visualize jitter
✓ Oscillators used in PLL – ring based – A case study
✓ PLL versus a Delay line
✓ Need of Phase Interpolation
✓ Need of Duty Cycle Correction
✓ Corner study – understanding of regular and skewed corners
Phase Locked Loops
• Generate periodic signals
• The signals have fixed time- period
In Voltage domain negative feedback In phase domain negative feedback
If loop gain is large , Vout ≈ Vin If loop gain is large , Φout ≈ Φin
Where do we need PLLs ?
1011000111001
Memory CPU
Data Rate = 10 Gbps = 10 10 bits / sec
How is this data rate kept in place ?
A clock both at TX and RX side will make sure that in every second, 10 10 bits are transferred
Clock period = 1/ 10 10 = 100ps
How to generate a periodic signal ?
Phase VCO
Detector
1. Initial imbalance / condition
2. Conversion of one type of energy into another
3. Sustaining mechanism
Pendulum – An oscillatory system
Inverter Based Oscillators
Can Oscillators generate perfect periodic output?
Noise in time domain and frequency domain
A noiseless oscillator generates a perfectly
periodic output
Noise sources disturb both amplitude and phase
What is Jitter ?
• The departure of the zero crossings of a nominally periodic waveform from their
ideal time points is “jitter”
• Jitter generally refers to a time-domain phenomenon.
Design of Inverter Based Ring Oscillators
Case Study : How to design a RO at 2 GHz ?
• Start with minimum-size devices and the minimum number of stages for any
technology eg: Lmin = 40 nm
Minimum Size – allowed by the technology, Lmin = 40 nm
Minimum stages = 3
Simulate and check at Typical corner at Room Temp with Vdd = 1V
Time period = 2 x τ x N
τ = rise to fall delay / fall to rise delay
How to calculate frequency for any technology node ?
1 1
FO4 delay for any tech node (5τ) = 𝑡𝑜 of technology node
3 2
Sample calculation
Observations for further design
• Tech node = 40 nm
1. Target is 2 GHz , and the frequency obtained is 42 GHz
• 5τ = 14 ps to 20 ps
2. Interconnect capacitance
3. Input capacitance of the subsequent stage/ load
• τ = 2.8p to 4 ps
4. Worst Case conditions of PVT : usually SS corner, Vddmin and Temp
• fosc = 42 GHz
Design in extreme conditions
1. Assume Interconnect capacitance : 0.2fF - 0.5fF to each node
2. Load of a buffer with FO1
3. At SS , 0.9V and Temp -5 / 125
What will be the observation ?
• Freq of oscillation will degrade as the delay will be more
• Size the inverters PMOS / NMOS depending on the waveform obtained at extreme corner case
• Measure current and check the feasibility
How to obtain the desired frequency ?
Reference design
• AT WC corner, assuming that the freq is 20 GHz
• To reach the desired frequency
a. Add cap to each node
b. Increase number of stages
c. Increase the length of transistors
d. Divide the output frequency by an appropriate factor
Method 1 : Add cap to each node
How to estimate the cap value ?
2
𝑃𝑜𝑤𝑒𝑟 = 3 𝑓 𝐶𝑡𝑜𝑡 𝑉𝑑𝑑
𝑓𝑝𝑟𝑒
𝐶𝑡𝑜𝑡,𝑛𝑒𝑤 = 𝐶
𝑓𝑑𝑒𝑠 𝑡𝑜𝑡
?
Observation
1. By adding caps, the target frequency will be achieved
2. Rise and fall delays have increased Whether Power is increased
Method 2 : Increase number of stages
Observation
1. Waveform exhibit sharper edges – original tr and tf
Whether Power is increased ?
𝑃 = 𝑁 𝑓 𝐶𝑡𝑜𝑡 𝑉𝑑𝑑2
1
𝑓=
2 𝑁𝑡𝑑
the three-stage and the 31-stage design draw approximately equal powers
Method 3 : Greater Transistor
How should we increase the transistor channel lengths ?
1. Inverters become weaker
2. Input capacitance arises
3. Flicker noise decreases
Observation
?
1. Longer rise and fall times
Power
Reduced by the same factor
Higher jitter / Phase Noise
Method 4 : Frequency Division
The divider consumes additional power
Observation
?
1. Rise and fall times will be better
Power
Divider consumes additional
power
Summary & conclusion of design strategies
3 2 1 4
Deterministic Jitter / Supply noise
Use of regulator reduces noise
Typical Scenario
Data 110000111100111 Circuit receives data Data
Clk
Clock Circuit receives clock
Clock arrives at right time Clock arrives early Clock arrives late
Need of clock with varying delay /phase
Clock arrives early
Need to delay it
Delay Line
do not provide a phase spacing less than one gate delay
How can we achieve higher resolution ?
clock
With one gate delay
Phase Interpolation
Higher resolution
Phase Interpolation?
two identical inverters can perform interpolation Interpolation by a factor of 2
Phase resolution is doubled
At t12, the NMOS transistor in Inv1 and the PMOS device in Inv2 are heavily on
For equal strength devices Vout @t12 = (VI + VQ)/2
Common Issue in Phase Interpolation?
Kink problem
if the input edge spacing, t2 – t1, is greater than the transition times of VI and VQ, then Vout suffers from a kink
Note :input transitions should be sufficiently slow to avoid kink
Duty Cycle Correction
Input duty cycle can deviate from 50% leads to degradation of timing margins in systems
𝑇𝑐𝑘 /2 + ∆𝑇
𝐷𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 =
𝑇𝑐𝑘
What should a DCC do ?
• Measure ∆𝑇
• Drive this ∆𝑇 to zero
What should a DCC do ?
• Measure ∆𝑇
• Drive this ∆𝑇 to zero
• ΔT ≠ 0, the average value of Vint continues to
rise (or fall), serving as a measure of the duty
cycle error
What should a DCC do ?
• Measure ∆𝑇
• Drive this ∆𝑇 to zero
• M3 and M4 can create an arbitrary difference
between the rise and fall times at X.
• If Vint is relatively high, M3 slows down the
rising edge. Similarly, M4 controls the falling
edge.
DCC
• Measure ∆𝑇
• Drive this ∆𝑇 to zero
Process Corners
• Refers to the variation of fabrication parameters
• (extremes of parameter variations within which a circuit can be etched onto a wafer)
• Corner lots are made to verify the robustness of an IC
• Group of wafers that have process parameters adjusted to extremes
• Characterization is done on corner lots
• varying increments of environmental conditions, such as voltage,
clock frequency, and temperature
Types of Corners
• FEOL corners
• BEOL corners
References
• Razavi – IEEE Solid State Circuits Magazine – The Design of a Phase Interpolator – 2023
• Razavi - Cambridge University Press - Design of CMOS PLL – From circuit level to architecture level – 2019
• A. Homayoun and B. Razavi - IEEE J. Solid-State Circuits - Relation between delay line phase noise and ring
oscillator phase noise, 2014
• E. Song et al - ,” IEEE J. of Solid-State Circuits - A reset-free anti-harmonic delay-locked loop using a cycle period
detector,2004
• Wikepedia
• Learnings from the projects
Thank You
