Modeling and Design of Spintronic Integrated Circuits
Modeling and Design of Spintronic Integrated Circuits
I. INTRODUCTION
The spin current can be also related to the velocity and spin D. Total Spin Current Vector
states of the carriers in a circuit/device. The components of the The total spin current is simply the combination of the charge
vector spin current are expressed as a sum over the momentum current and vector spin current. It is a 4 1 column vector.
states of electrons, normalized to density of electrons
(5)
(2.1)
The ratio between the charge current and the magnitude of the
spin current is the current’s spin polarization ratio
where are Pauli matrices, is cross sectional area, is the
velocity component normal to it, and is the spin density matrix.
It is defined with the negative sign to reflect the negative charge (6)
of electrons, similarly to the electric charge current
(2.2)
E. Total Spin Voltage Vector
This way, the spin current corresponds to the flux of magnetic The total spin voltage vector is the combination of the
moments. Thus, in Fig. 1(a), the electrical current (blue arrow scalar columbic potential and the vector spin potential. It is a
to the right) is opposite to the flux of electrons (red arrow to the 4 1 column vector.
left. If the net spin projection is positive, then the spin current,
blue arrow in Fig. 1(b), is opposite to the flux of electrons (red (7)
arrow).
The ratio between the scalar potential and the magnitude of the
C. Vector Spin Voltage spin potential is the voltage-spin polarization ratio of a node.
Vector spin voltage at a node
(8)
(3)
where G is the 4 4 conductance matrix: is directly proportional and collinear to the vector spin voltage
difference applied to the NME, i.e.,
(13)
(10) (14)
(16)
where is the set of all node pairs in a given closed loop.
Fig. 5. Circuit model for spin transport between a ferromagnet (FM) and a
normal metal (NM). The entire FM is treated as a node with a specific vector
spin voltage.
Fig. 3. Conservation laws for spin voltages and currents. (a) The sum of loop
voltage differences is zero. (b) The sum of the physical spin currents from all
physical branches is equal to the spin flip current to a virtual ground.
4 1 spin voltages at the FM and NM be and
respectively. Here for simplicity we ignore
the spin accumulation in FM. Let be the 4 1
spin current from FM to NM and be the vector direction of the
magnet’s magnetic moment. Then, according to [38], the charge
current is
(19)
TABLE III
NANOMAGNET PARAMETERS FOR SPIN CIRCUIT THEORY USED IN
COMBINATION WITH A MACROSPIN NANOMAGNET MODEL
Fig. 6. Circuit model for spin transport between a ferromagnet (FM) and a
normal metal (NM). The FM magnetization can point in any direction in three
dimensions as determined by the nanomagnet dynamics.
TABLE I
LIST OF VARIABLES FOR SPIN CIRCUIT THEORY
(28)
TABLE II (29)
TRANSPORT PARAMETERS USED IN SPIN CIRCUIT THEORY
(30)
(31)
(32)
Hence, the generalized Ohm’s law for the FM-NM interface is
[18]
VI. SELF-CONSISTENCY OF NANOMAGNET DYNAMICS
WITH SPIN CIRCUIT ANALYSIS
We now describe a coupled spin transport-magnetization dy-
namics model [76] for solving spin integrated circuits which
employ nanomagnets for spin injection. The phenomenological
(26) equation describing the dynamics of nanomagnet with a mag-
Since (19)–(22) are independent of the orientation of the inter- netic moment unit vector , the modified Landau-Lifshitz-
face, we can extend by induction that the same expression for Gilbert (LLG) equation [49], [50], with spin transfer torques in
the conduction matrix is valid for any direction of magnetiza- the form of [38] is (see Table III for parameters)
tion provided that the coordinate system has its x-axis aligned
to it, (33)
TABLE IV
SPIN MNA MATRICES
TABLE V
PARAMETERS USED FOR EXAMPLE CIRCUIT SIMULATION
Fig. 9. A lateral spin logic device comprising two nanomagnets and nonmag-
netic channels. Channel connecting 1–2 acts as an interconnect between the two
magnets transporting spin polarized currents. (a) Top view of spin logic device.
(b) Side view of a lateral spin logic device. (c) Netlist of the circuit that can be
parsed by a spin-MNA algorithm. (d) Circuit model of spin logic device.
A. Example Spin Circuit: Numbering the Nodes, Forming
Spin Netlist
We model the device as a spin circuit comprising of two nano-
as an inverting gate for positive applied voltages and a nonin- magnets and nonmagnetic conductive elements. The nonmag-
verting gate for negative applied voltages. netic elements model the behavior of the metal channels con-
Intuitively, the operation of the device can be explained as fol- necting the magnets to each other and to the ground. In Fig. 9,
lows: the magnets create spin polarized population densities un- we show the top view and side view of the device. We choose
derneath the magnets and setup spin diffusion currents through the node-0 to be the ground and number the remaining nodes as
the channel. The direction of this spin diffusion current is set per the convention of MNA. Node 1, 2 represent the points in
by the relative strength of the spin polarization of the carriers. the device just below the magnets representing the ends of the
For a ground terminal set near the input magnet it can be shown channel. Node 3 is common node shared by the magnets and the
that the magnet 1 acts as a fixed magnetic terminal, while the supply. We can now derive the circuit diagram for the device
second magnet responds to the spin diffused to beneath it, de- as shown in Fig. 9(d). The magnetic elements are represented
pending on the applied voltages. For a positive applied voltage, by ; the nonmagnetic channel is represented by a
the device shown in Fig. 9 acts like an inverting gate, where the -equivalent circuit as described in Section IV-D. The ground
output becomes a logical invert of the input. For negative ap- connection branch is represented by a T equivalent circuit.
plied voltages, the output becomes a copy of the input magnet’s The assumed dimensions and the list of variables are shown in
condition. The sectioned structure of the channel is required Table V. We show the netlist for the device in Fig. 9(c).
to isolate spin logic gates, where the interconnection between
gates (concatenation) is achieved via a continuous free layer B. Example Spin Circuit: Forming the MNA Equation
magnet. The nonreciprocity of (output to input signal transport)
spin logic comes from an asymmetry between input and output Using the rules described in Appendix H, we can build the
magnets. This asymmetry can be achieved via: a) an asymmetric spin-MNA equation for the circuit in Fig. 9(d) as follows: the G
overlap of the magnet such that the area of the output is smaller matrix is filled with the spin conductivity elements connecting
than the area of input magnet; b) asymmetric ground condition; to nodes 1–4. The elements representing connectivity (5,3) is
c) asymmetric spin injection efficiency (Fig. 9); d) asymmetric filled with an identity matrix such that the applied voltage at
spin damping constant. node 3 is . The row 3 represents the KCL at the node 3 and
2808 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 12, DECEMBER 2012
(38)
(39)
(37)
MANIPATRUNI et al.: MODELING AND DESIGN OF SPINTRONIC INTEGRATED CIRCUITS 2809
(A2)
(A3)
(A21)
(A4)
The conductance for the parallel branch of the network is
where the conductivity is , and the spin diffusion length is
. A general solution for these equations is
(A22)
(A5)
APPENDIX B
where the boundary conditions set the coefficients , . The spe- TO T EQUIVALENT CIRCUIT TRANSFORMATION
cific solution for the uniform conductor of length is
Spin-dependent conductance with spin relaxation can be
equivalently represented by -shaped [Fig. 4(b)] or T-shaped
(A6)
[Fig. 4(c)] networks. Here we derive a general relation between
(A7) these two approaches.
In both cases the vector voltages at the terminals, V1 and V2
are the same. In the -network, the spin-relaxation currents are
(A8)
(B1)
(A9) (B2)
2810 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 12, DECEMBER 2012
and the current passing through the center conductance is conduction matrix elements of a FM as phenomenological
constants extracted from experimental properties of the
(B3) FM-NM conduction. Here, we provide a description of the
conduction matrix elements of a FM that is derived from an ab
They are related to the total currents entering and leaving the initio approach [18], [38]. The conduction matrix
network as follows:
(B4)
(C1)
(B5)
The voltage at the middle node is thus related (for nonzero spin
relaxation) to the in- and out-currents (C5)
(B12)
where is the conductance per spin of a ballistic channel
As before, we express via the unity matrix with ideal contacts [38]; , are the transmission coeffi-
cients for up and down spin electrons from NM to FM; ,
are the reflection coefficients of the up and down spin elec-
(B13) trons at the FM-NM interface; is the number of modes in the
NM, is the number of modes in the FM. The number of modes
(B14)
in a metal can in-turn be written from the metal’s Fermi
Since the two expressions for in- and out-currents should be wave vector [48].
equivalent, the following relations between nonzero conduc- It has been argued that , are close to zero for many
tances must hold: material systems [38], which simplifies the spin torque conduc-
tance to to
(B15)
(B16) (C6)
APPENDIX F
(D3) STOCHASTIC LLG EQUATIONS
(D4) THERMAL NOISE OF NANOMAGNETS: The dynamics
of nanomagnets are strongly affected by the thermal noise.
In the new coordinate system
Thermal noise in a nanomagnet manifests as fluctuations to the
(D5) internal anisotropic field [51]–[54]. The thermal noise can be
considered as a result of the microscopic degrees of freedom
where is the matrix described in Section V. Let us substitute of the conduction electrons and the lattice of the ferromagnetic
element [51].
(D6) At room temperature T, the thermal noise is described by a
(D7) Gaussian white noise (with a time domain Dirac-delta auto-cor-
relation). The noise field acts isotropically on the magnet. In
and rearrange to obtain the current, voltage relation in the xyz presence of the noise, the LLG equation can be written as
co-ordinate system. We obtain
(D8)
(F1)
Hence, the conductance matrix for an FM with magnetic mo-
ment along an arbitrary direction is given by where we modified (33) by adding temperature dependence. The
internal field is described as
(D9)
(F2)
APPENDIX E (F3)
CONVERSION FROM SPINOR BASIS TO VECTOR BASIS
(F4)
Conversion Between Spinor Spin Current/Voltage Basis to
4 Component Vector Current/Voltage Basis: The derivations
for magneto-electronic circuit theory are often performed in the The initial conditions of the magnets should also be random-
spinor basis for the electrons [39]. For convenience we list the ized to be consistent with the distribution of initial angles of
conversion from spinor basis to Cartesian vector basis as well magnet moments in a large collection of magnets. At tempera-
as 4-component current basis. The current in a spinor basis can
ture T, the initial angle of the magnets follows [52]
be written as [39]
(F5)
(E1)
where is the Pauli spin matrix NUMERICAL METHODS FOR STOCHASTIC LLG EQUATIONS:
An accurate choice of the method for integration of the sto-
(E2) chastic LLG equation is essential since: a) the stochastic differ-
ential equations (SDE) require careful handling of the order of
integration [67], [68]; b) a multiplicative white noise requires
which yields
an appropriate choice of calculus [53], [69]. The appropriate
model for direct integration of SDE are usually first order in-
(E3) tegration methods such as Euler & Heun. Even though higher
order methods have been proposed in the literature, the accu-
Hence, the 4-component current vector can be derived from the racy and applicability for realistic SDEs have been questioned
spinor current as follows: [67], [68]. Hence, a first order integration method with a fixed
time step is generally recommended [53].
Secondly, Stratonovich calculus is used for interpreting the
multiplicative white noise. We used a mid-point integration
(E4) method [53] to apply the Stratonovich calculus while inte-
grating the LLG equation. The discretized integration rule is
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Sasikanth Manipatruni (M’07) was born in Ian. A. Young (M’78–SM’96–F’99) was born in
Vizianagaram, India. He graduated from Indian Melbourne, Australia. He received the B.S. and M.S.
Institute of Technology (IIT) Delhi at the top of degrees in electrical engineering from the University
his class in electrical engineering in 2005 with the of Melbourne, Australia, in 1972 and 1975, respec-
best hardware thesis project award. He received tively, and the Ph.D. degree in electrical engineering
the Ph.D. degree from Cornell University, Ithaca, from the University of California, Berkeley, in 1978.
NY, working with Prof. Michal Lipson in silicon Prior to Intel, Dr. Young worked on analog/digital
photonics and opto-mechanics. During his Ph.D., he integrated circuits for Telecommunications products
was co-inventor of several silicon photonic devices at Mostek Corporation (United Technologies Corpo-
including the first 18 Gb/s micro-ring modulator, ration). He is a Senior Fellow and Director of Ex-
first GHz poly-silicon modulator, hitless broadband ploratory Integrated Devices and Circuits group in
EO switches and integrated silicon nanophotonic link. Intel Components Research, Technology and Manufacturing Group at Intel Cor-
He was previously at General Electric (GE) Global Research Center working poration, Hillsboro, OR. He is responsible for defining and developing future
in nanophotonic interconnects for massively parallel magnetic resonance circuit directions with emerging novel devices and identifying leading options
imaging (MRI) and demonstrated the first analog-RF optical MRI system at for devices and interconnects to manufacture solid-state integrated circuits in
3T magnetic fields. He joined Intel, Hillsboro, OR, in 2011. He is a Research the post-CMOS era. He joined Intel in 1983. Starting with the development of
Scientist in the Exploratory Integrated Devices and Circuits group in Intel Com- circuits for a 1 Mb DRAM, and the world’s first 1 64 K SRAM, he then led
ponents Research, Technology and Manufacturing Group at Intel Corporation. the design of three generations of SRAM products and manufacturing test vehi-
He is working on emerging novel devices to identify technology options for cles, and developed the original phase locked loop (PLL) based clocking circuit
beyond CMOS logic technologies. He has more than 10 patent applications in in a microprocessor while working on the 50 MHz Intel 486™ processor design.
nano-photonics and MRI, and 40 peer reviewed journal and conference papers. He subsequently developed the core PLL clocking circuit building blocks used
Dr. Manipatruni was a KVPY national science fellow of the Indian Insti- in each generation of Intel microprocessors through the 0.13 3.2 GHz Pen-
tute of Sciences (IISc) (1999–2001); worked at Swiss Federal Institute of Tech- tium 4. Dr. Young has developed a number of optimization metrics for process
nology (ETH), Zurich in 2004; and Inter University center for astronomy and technology development, including the transistor performance metric that pro-
astrophysics (IUCAA) in 2001. He serves as a peer reviewer for OSA, IEEE, vided a link between processor performance and basic transistor parameters, as
and Nature Photonics. His business plan for fab-less photonics was awarded well as back-end metal interconnect architecture. He holds 55 patents in inte-
the first place in Asia-Pacific at Asia Moot Corp 2008 and selected as an out- grated circuits and has authored or coauthored over 50 technical papers.
standing product at World Moot Corp 2009. Dr. Young was a member of the Symposium on VLSI Circuits Technical
Program Committee from 1991 to 1996, serving as the Program Committee
Chairman in 1995/1996, and the Symposium Chairman in 1997/1998. He was
a member of the ISSCC Technical Program Committee from 1992 to 2005,
Dmtri E. Nikonov (M’99–SM’06) received the serving as the Digital Subcommittee Chair from 1997 to 2003, the Technical
M.S. degree in aeromechanical engineering from Program Committee Vice-chair in 2004 and Chair in 2005. He was Guest Editor
the Moscow Institute of Physics and Technology, for the April 1997, April 1996, and December 1994 issues of the IEEE JOURNAL
Russia, in 1992 and the Ph.D. degree in physics from OF SOLID-STATE CIRCUITS. He has served as an elected member of the SSCS
Texas A&M University, College Station, in 1996, Adcom from 2006 to 2009. He received the International Solid-State Circuits
where he participated in the demonstration of the Conference’s 2009 Jack Raper Award for Outstanding Technology-Directions,
world’s first laser without population inversion. for the paper entitled “Optical I/O Technology in Tera-Scale Computing.”
He joined Intel Corporation in 1998 and is
presently a Research Scientist in the Components
Research group in Hillsboro, OR. He is responsible
for simulation and benchmarking of beyond-CMOS
logic devices and for managing joint research programs with universities on
nanotechnology and exploratory devices. From 1997 to 1998 he was a research
engineer and lecturer at the Department of Electrical and Computer Engineering
of University of California Santa Barbara. In 2006 he was appointed Adjunct
Associate Professor of Electrical and Computer Engineering at Purdue Uni-
versity. He has 60 publications in refereed journals in quantum optics, lasers,
nanoelectronics and spintronics, and 35 issued patents in optoelectronics,
integrated optic and spintronic devices.
Dr. Nikonov was a finalist of the Best Doctoral Thesis competition of the
American Physical Society in 1997.