Assignment Questions
Assignment Questions
1. Define Moore’s law and explain its implication on IC industry in terms of cost, feature
size and performance.
2. With a neat diagram explain the MOS structure
3. With a neat diagram illustrate the concept of CMOS logic and describe the working of a
CMOS inverter.
4. Draw the schematic of a 3-input and 2 input NAND/NOR gate using CMOS technology
and explain its operation with the help of a truth table.
5. Explain pass transistors and transmission gates in CMOS logic circuits?
6. Sketch CMOS compound gate for function Y= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(A + B + C) · D)
7. Describe the step-by-step process of fabricating a CMOS transistor.
8. What are stick diagrams in VLSI design? Create a stick diagram for a simple inverter/
three input NAND
9. Sketch a stick diagram for a CMOS gate computing Y = (A + B + C) · D)’ and estimate
the cell width and height.
10. What is lamda based design rules and explain in detail with neat diagrams
1. Explain the structure and operation of an nMOS transistor in accumulation, depletion, and
inversion modes. Illustrate with relevant diagrams.
2. Illustrate the DC transfer characteristics of a CMOS inverter. Explain the regions of
operation of nMOS and pMOS transistors in the inverter circuit.
3. Describe the MOSFET current equation in the linear and saturation regions. Derive the
equation for drain current (Ids) and explain how it varies with Vgs and Vds.
4. Explain the concept of noise margin in CMOS circuits. Describe with a neat diagram.
5. How does the beta ratio (βp/βn) affect the threshold voltage and output of skewed inverters?
What is the difference between HI-skewed and LO-skewed inverters?
6. Explain the operation of transmission gate? Discuss the advantages of transmission gate
over pass transistor logic
7. With a neat circuit diagram explain the tri state inverter
8. Illustrate the working of nMOS inverter with resistive load and draw the I-V characteristics
and transfer characteristics.
9. Draw the pseudo- Nmos Inverter circuit and sketch the transfer characteristics
10. How do nMOS and pMOS transistors handle passing 1s and 0s in terms of threshold voltage
drop, and how does this affect signal degradation when multiple transistors are in series?