EDDITED
EDDITED
The logic block maps the digital ADC input to a scaled value for further calculations and
applies the DAC-ADC back-to-back transformation:
1. Scale p (ADC digital value) to x in the range [−10,10] based on the given resolution.
2. Map x back to p for DAC output.
𝑥=( 𝑝
∗ 20) − 10 (5)
4095
Code:
#include “F28x_Project.h”
#define ADC_MAX 4095 // Maximum ADC value (12-bit ADC)
#define X_MAX 10.0 // Maximum x value
#define X_MIN -10.0 // Minimum x value
#define DAC_MAX 4095 // Maximum DAC value
float map_adc_to_x(uint16_t adc_value)
{
// Map ADC value to x in the range [-10, 10]
return ((float)adc_value / ADC_MAX) * (X_MAX - X_MIN) + X_MIN;
}
uint16_t map_x_to_dac(float x)
{
// Map x back to DAC range [0, 4095]
return (uint16_t)(((x - X_MIN) / (X_MAX - X_MIN)) * DAC_MAX);
}
// Example usage in the ISR or main loop
interrupt void epwm_isr(void)
{
uint16_t adc_value = AdcaResultRegs.ADCRESULT0; // Read ADC value
float x = map_adc_to_x(adc_value); // Map ADC to x
// Logic block implementation
// Perform any intermediate computation or scaling (optional)
uint16_t dac_value = map_x_to_dac(x); // Map x to DAC value
DacaRegs.DACVALS.all = dac_value; // Write to DAC
// Clear interrupt flag
EPwm1Regs.ETCLR.bit.INT = 1;
}
Ans (iii)
Code:
#include “F28x_Project.h”
// Write to DAC
DacaRegs.DACVALS.all = dac_value;
EPwm1Regs.ETCLR.bit.INT = 1;
Ans (iv)
Code:
#include “F28x_Project.h”
// Calculate p for x = 5
DacaRegs.DACVALS.all = p;
Ans (v)
Modify C(s) in real-time (using watch variables) and observe the impact on y. Comment on
whether the system stabilises or oscillates.
Ans (vi)
Code:
#include “F28x_Project.h”
#define TIMER_PERIOD 1000000 // Timer period for 1 Hz (assuming 100 MHz clock)
if (z < Z_TARGET) {
} else
CpuTimer0Regs.TCR.bit.TIF = 1;
void init_timer(void) {
}
// Placeholder function to compute z based on C(s)
float compute_z(float C) {
Ans (vii)
Code:
// Update x
x = new_x;
DacaRegs.DACVALS.all = p;
// Measure y