Page No.

(
MANJARA CHARUTABLE
RAJIV TRUST
GANDHI INSTITUTE TECHNOLOGY, MUMBAI
JUHU VERSOVA OF
LINK ROAD, VERSOVA,
ANDHERI (WEST), MUMBAI53
Ass ignment

simelify 2implement Ahe

|0in9 fo

4n(lir,l,7lll2|13|5).

As

AB 2

Stepz patrs 90uping

) Cett,S)4up 1 (iDcels(S, 7)4u
(1)ceMs (12,130 qrou 2

34eesLogic diagram:

ABC

AGT

ACO
 MANJARA C
MU.
OF TECHNOLOGY, 53.

GANDHI INSTITUTE
VERSOVA, ANDHERI
(WEST), MUMBAI-
RAJIV JUHU VERSOVA
LINK ROAD,

ftwirh

Q)hat ou men
qnd l69íe dtag
ra
by
rht2
fu1 Qu bbractor Qplain

the subrathen
that coonpputer
Co m bin ati onal lo9iccircuit Subatr
o full
tnYee binay'digitrscalled
T4 has 3 input 20utputsAL ptt >Bout
|Truth table
SusTeAttOP

A Bin ftrtnce (DD BoroslBut

-lolol--ood
E-oooo>p
k Map tr (ference oAiithy9Vib2

A D A sin

k Map tor Bao

 Logic dta qram.

A
EX A BBin
Oiffeenle

An

AB Aßin+ AB+
BBin

B8in

O Ioplement the -fo||bulng boolean ezpression using 4i muz

Step4! Prepave implementaton feble (man terms

D D D6
A
A 2 13) ((4)
A A A A
 VERSOVA, ANDHERI (WEST), MUMBAI
JUHUVERSOVA LINK ROAD,

DA

8 S So F(PQR)
StSo

Q)Tmplement the fo |luwing Boolean fun eticn using 1

multiplexer fCA BCD) m

lb,l,4,5, G3l0,12,13).

Step1 t pareimple mentatt entable cmninterm)

Do Pu
A o)e )
A' a
A
A
A

Dr
 binary to2 bit yaytodr tonsorter uring 3h
O5) Derlgn a 3 bit

oL4atn tnuth 4abte of

4.2 docoder
S ees To

JiptsOtpuke
64B

Go2m l,2 S,6)

tfuliad dey
LStep4 toostálotnth tasle
couteutt
t*

step2!CU Nnect funchon vaiablein input

Inputs
Ae Cin CamySum Q4ep3. Imptmentati on
 MUMBAI- 53
RAJIV JUHUVERSOVA LINK ROAD,
VERSOVA, ANDHERI (WEST),

methods' symbols of
tip opr
07)Platn varous tigqerinq
As drbuted to all partt of the tiruit
stgnal is
Tgeerng' he clock
and mbst outputt changésta e ony
when clock makee
h

fretn positive fo
ttansition. The transii n of clock signa
nega ive o vice veya s known as Tigge ving
a) Pulre trig9en'ng'
Jfosive pulse: A waveform in which the normod state s
oqtt O e changes to logtc 1 momentaily to (odyca a clot ue
n) Negahve pulte.A Loqve for m in which the norma s tate ir log fe
1 Rchanger to (bqic D mnome mtany to prod uee a clock pulre.

+ve
Putse Pulse

T)EDGt TRIG GEP|NG' Tt neans the o tput state chan ger e fther
at the posiH ve edge or at neg a ivé dgeot
pulye. clock
a)Posittve edgeOutput responds to the changer in the input
only at tht positivel edge of the etoek p alse at theclo(kingut
5)Negafve edge:Outpu b rea theto theh'anges in the ingut nly at
the negaHve edge rof (lock pulse iat elbck i neyt
àve eege

TY EVEL TRIGGtRiwG. Tn level tnggerìng the

output Stete can
change atcordina to input hen achivè levetleithertve r
ve) S maintatned qt
enable input The re ate two tyre
o)Posi hve teadioutput offieflop
responds to the input
Change onty when its enable orctock nput (s 4CHRr9h)
 RUAD, VERSOVA, ANDHERI WEST MUMBAI-$3

tb)Neg ative teval *otput bt ft eftopse esprrn t 3 n t charges

nlye'n its enaeaeto(k putro in )
1evel

Qwnat is shift vegistos plain in details ditfe rert types

at shift registe ks lomg wth dota mdvenents.
So1m
TShift veqts tevavt qvoupof tisftops ohich sused tostove
multiele cbits ot datathel tata is govedfrun ne fip lop
NNto another t)altiEw sdle
T9re of shifFt'veqis tevsyzi osleg1o
)semal in- sévial'out:In cerial in- serial out shit egis tu
(right shift) the data bit art hifted from left to right
by1 positionduring eachitock
Cucle senad,thss serial data
data in putFoFf1FF 2Ff3 utp ut (left t righ
c Thne data tApts bitstn serialcin Cenal out;lett shift
veaistr from right to lett by 1 positto n dunng clokey cte
seriat5ire seriad data input

)Seriee in parallel out: Inseialgin-paraltelioutshif

Vegister aUtRuts i|k beavatlable attr 4ctoclc

pulses for a Gblt shiftieqtster9 ie ktue

date fo
Ti4
tFfff2tttui
Q2
Pavalle) data output
 JUHU VERSOVA LINK ROAD VERSOVA,ANDHERI (WEST), MUMBAI 53

2) farallelinserial-out
npa tatlel geñal out
egrtr allthe shiftreqLsterin putt aeloaded sh
Simultane ously but shrft veqster
outp ut ae loeded
Lit by bit
seially

ffo

dat travel.
4 ParalleiTn-paralfel
shiftouti tere all theshife
reaisttr 'inputs de qddedr a Sim
outputs lll be avail able uttaneoübly'a nd all
ne lotk Si
mutan eousyle only
pulse is req ured
tóilead alU the bitt
Parallel da ta ineuts

faralleata outfut
Cha) cmpare g4nchrono us
Counteroith tisynchonos
Countr
4uyriltrfsynhronu9 Counter
1 Symch ronous
(ounter tn üh
chettyn Counter
clock is applied to omly theadncounterinwhich
6f all
clock inpus
fipftop ate
tfrettop and sutcess{ve 5
insynch
1
3o11toeS bithech other nd can
e
lockedy te tae'red b be
output of y'eternal
pevios fiptop elock
2)simple logie icuit
Sigm al292lt
2) Complex 1o gtc circuib
3)47 tt pftops qenot
ttocked 2)
imutaneously
ALtptopS are e(oched
simultaneously
 JUHU VERSOVA LINK ROAD,VERSOVA,ANDHERI(WEST), MUMBAI-53.

pd= N xtpd of1-rftop

Matmum operatng frequenty s)mantmum o perating reuenty i high
1s lou'due tolowropogatton dela 9 ldue to short propog oattom de (ay
6) Lere (ost )More cost
Asoknowna lavatley
Se vtes fipeleountere Counterk
)utputiof previoes ipftu R-nere (s no lonnecHeni betoeen

D)More decodtg erroY (o)Le4s delod ing errer

)Invaltd state at by pasted 1)Tnvalrd sta test ate constder by
feod back beaing ofecitationg
A0 by provifàtng
12)Less Cirutsi? ol 12) more ctrealtI45
13) G frthes isian išadvantage0

o1pIHererrttatt betoeeno Stati Dynamic RAM memory.

YYC yna mtc PAMime mory

)each geAM el is.attettor acK'D PAM unit comsist ef one
mos fET& Capacitor

k1 Dmoe noot Compoments er) Less noot Compements per

Cell

) Memony cetls (essthan DPAM r)Meonony cetls mae than SeAM

9 Reeeshing not required)Pe tre hing equired

9) More cot
 time

011) platnthe qéneol arhite raetu me, op cpLO!if

Som
Aomple 'ogra'mable Cog Dete Salogi devica
h moggmabte AnD anray loea'ray macvoetls fe
iveuits, that needamore snmber0fn put ¢oatp uti and
pvo d'termitheicap acityo/thes eDs Às.expa nded
àtt
by cascading thenin c chip tnat is known as cpl0.D

toi LOstonivt5
CPLD'si Cani locstáltd to large sire layincreastng no of PLos
POtyI can ntegratefun ctong anurovern of Splonto single
device. They aeprog va mmed u ine in syrtem progra mmingP)
f CombMerarenite ctuvat featu ves so P Ab'sFicA It
Poides well stuctua enera archtectue of nu Ynbes of (og s
blbeCs and a proqram rnHrconnett h2 n
TEnal grammable ANDoR arys m acmosCellg.
Z0 Cells

YOgammabie
 XC9S72CpO: XLehYces00pafamly of ceLA 1nterna

ile limaCYocell 18 outrut o1tteated 36 v13 devi

The devies in thel famity are namedagtortng to number
t malrbeells tn the ontutns They ate hig h pe rtr mane,

ot ,Ooprqvamenhaned pin locken arehie (ure Go bat

prody tt trm elok, utut enab1es set &reset

Q12 ohat is VHOL? oit entiu dectQra ti on program fbr full

adder tituits

NDL Stands fr veny high Seed Integrated eruit (VHSTO

hardware lescriptn anguageIt Used to tan adegtet
Systm many 1evelsof ahsretion
at ranggrem algithe
oqate levetIdetineo the ntax allas stimulain
Semantics f lqnguage

FeatuHe
1)(om crrentyvHO iS Con current \anquageecutes
Conturent stattmert stmutaneously.
lb) IE
ured tordes tgn entry stmltaneod d tgtt cereuti
B) It Suppots seguential stuttment: vHOL can e ecufe one
Statment at a time
4)Suppovts a design
libray.
It allocos tecting t stimu lattn of ra me. mg
6) T4 s ston gly tyred (anguage my LHo&es ere etos
ot cane ty ee are a|lowed
 Ustna oU hieravhy can bieHep1ented 'ei a tull
adteY Can berconsthucted ueitna too ad ders and me

)TtSLRPor man levekr of abstraCt on t

tre,l entity Dtaaram fe futliad d ei cruit esr

B
Zoput] 4outeut

BLock D1AGRAM

ntity full adder s

P ont CA B Cin :in bie ho1

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