1. How does A Latch get inferred In Rtl Design?

 When there is no “else / default” statement in the “if / case” statements; in

short, if all possibilities of the conditions are not covered.
 When all the outputs reg is not assigned the values in every condition of the “if /
case” statement, and some are left out, on the left-out signals, a latch gets
inferred.
2. Does A Latch Get Inferred When There Is No Else Statement But
Multiple Ifs Covering the Whole Functionality?
Conceptually, no latch should be inferred, but sometimes the synthesis tools are
not intelligent enough, and they might infer a latch. In order to avoid that, the
safest way is to use an “else / default” statement in “if / case” respectively.
3. If There Is An Asynchronous Feedback Loop, What Is The Problem?
If there is an asynchronous loop in the design, the circuit becomes oscillatory, or
it may reach a stable state where it might get hung, and it cannot get out.
4. If An Oscillatory Circuit Is There; What Happens During (a) Rtl
Synthesis (b) Simulation?
 During the RTL synthesis, the synthesis tool will give a warning during synthesis
about the combinatorial feedback loop.
 During the simulation, the simulation will get stopped, saying the Iteration limit
reached.
Analog Communication Tutorial
5. Where Can We Use Linting Tools? Can We Use Them To Debug Syntax?
Linting tools are used to evaluate the design for the synthesizability of the design.
These tools are used to check for potential mismatches between simulation and
synthesis. No, they are not used to check the syntax.
6. What Can Be Done To Break The Combinational Loop?
By adding synchronous elements in the path. If it is really needed and if the
design permits then by adding the buffers in the path.
7. Why We Use B.A (blocking Assignments) And NBA (Non-Blocking
Assignments)?
B.A is used to model combinatorial logic as the value is of continuous assignment
and doesn’t depend on the previous value, while N.B.A is used to model
sequential circuits as the previous value is needed to propagate.
8. What Will Be The Output Of The Following Code?
Always ( * )
Begin
A = B + D;
A = C + B;
End
This is actually a race condition, and the tool will take the last assignment on “a”.
 9. Is There A Latch In The Following Code? What If The “sel” Value Is
“x”. What Will Be The Simulation Result?
Always @ ( En )
Begin
Dout = 0
Case ( Sel )
0: Dout = In ;
End
No There is no Latch as dout=0 before the case statement will be executed. Even
if the “sel” value is “X”, no latch would be formed as “dout” has been already
initialized to “0”.
10. Is There A Latch In The Following Code? What If The “sel” Value Is
“x”. What Will Be The Simulation Result?
Always @ ( En )
Begin
Dout = 0
Case ( Sel )
0: Dout = In ;
Default : Dout = 1;
End
No. There is no latch as the default statement is present, and the output will be
governed by the case statement.
11. If there are No Parameters In The Always Sensitivity List, How does
The Always Block Execute?
It will repeat itself like a forever loop but the performance will degrade.
Application Security
12. Tell The Scenarios Where Synthesis Error Occurs.?
A synthesis error can occur in the following scenarios:
 When there are multiple assignments on the same signal in two different
blocks, “a multiple driver found” message will come.
 When there is a mixture of asynchronous reset with some other signal, and that
signal is not used in the sensitivity list, basically, mixing of multiple edges and
synchronous and asynchronous elements are not allowed.
 No element in the always block sensitivity list.
 Mixing of B.A and NBA on the same signal in two different conditional
statements.
 If reg datatypes are used in assign statements, etc.

13. Is The Following Code Synthesizable?

Always @ (posedge Clk1 Or Negedge Clk2
)
Begin
If (!clk2)
Dout
 Else
Dout
End
Yes, it is synthesizable. Try to read clk2 as active low reset.
14. Are The Following Codes Synthesizable? Is There Any Difference In
The Synthesis results of (i) And (ii)?
(i) Always @ (posedge Clk1 Or Negedge Clk2)
Begin
If (!clk2 && A)
Dout
Else
Dout
End
(ii)
always @ (posedge Clk1 Or Negedge Rst)
Begin
If (!rst && A)
Dout
Else
Dout
End
Both are not synthesizable as there is a mixing of asynchronous and synchronous
element in the if condition.

Verilog Interview Questions

1. Write A Verilog Code To Swap the Contents Of Two Registers With And
Without A Temporary Register.
With temp reg ;
always @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end
2. Difference Between Task And Function?
Function:
 A function is unable to enable a task; however, functions can enable other
functions.
 A function will carry out its required duty in zero simulation time. ( The program
time will not be incremented during the function routine)
 Within a function, no event, delay, or timing control statements are permitted

 In the invocation of a function, there must be at least one argument to be

passed.
 Functions will only return a single value and cannot use either output or inout
statements.
Tasks:
 Tasks are capable of enabling a function as well as enabling other versions of a
Task
 Tasks also run with a zero simulation; however, they can, if required, be
executed in a nonzero simulation time.
 Tasks are allowed to contain any of these statements.

 A task is allowed to use zero or more arguments, which are of type output,
input, or input.
 A Task is unable to return a value but has the facility to pass multiple values via
the output and inout statements.
3. What is the difference between Inter-Statement And Intra-Statement
Delay?
//define register variables
reg a, b, c;
 //intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
4. Difference Between $monitor,$display & $strobe?
These commands have the same syntax and display text on the screen during
simulation. They are much less convenient than waveform display tools like
waves. $display and $strobe display once every time they are executed,
whereas $monitor displays every time one of its parameters changes.
The difference between $display and $strobe is that $strobe displays the
parameters at the very end of the current simulation time unit rather than
exactly where it is executed. The format string is like that in C/C++ and may
contain format characters. Format characters include %d (decimal), %h
(hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m
(hierarchy level). %5d, %5b, etc., would give exactly 5 spaces for the number
instead of the space needed. Append b, h, o to the task name to change the
default format to binary, octal, or hexadecimal.
Syntax:
$display (“format_string”, par_1, par_2, … );
$strobe (“format_string”, par_1, par_2, … );
$monitor (“format_string”, par_1, par_2, … );
5. What Is the Difference Between the Verilog Full Case And the Parallel
Case?
A “full” case statement is a case statement in which all possible case-expression
binary patterns can be matched to a case item or to a case default. If a case
statement does not include a case default and if it is possible to find a binary
case expression that does not match any of the defined case items, the case
statement is not “full.”
A “parallel” case statement is a case statement in which it is only possible to
match a case expression to one and only one case item. If it is possible to find a
case expression that would match more than one case item, the matching case
 items are called “overlapping” case items, and the case statement is not
“parallel.”
6. What Is Meant By Inferring Latches, how To Avoid It?
Consider the following :
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2’d0 : out = i0;
2’d1 : out = i1;
2’d2 : out = i2;
endcase
in a case statement, if all the possible combinations are not compared and the
default is also not specified, like in the example above, a latch will be inferred; a
latch is inferred to reproduce the previous value when an unknown branch is
specified.
For example, in the above case, if {s1,s0}=3, the previously stored value is
reproduced for this storing, a latch is inferred.
The same may be observed in the IF statement in case an ELSE IF is not specified.
To avoid inferring latches, make sure that all the cases are mentioned if no default
condition is provided.
7. Tell Me How Blocking And Non-Blocking Statements Get Executed?
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side
expression) of the blocking assignment without interruption from any other
Verilog statement. A blocking assignment “blocks” trailing assignments in the
same always block from occurring until after the current assignment has been
completed
Execution of nonblocking assignments can be viewed as a two-step process:
Evaluate the RHS of nonblocking statements at the beginning of the time step.
Update the LHS of nonblocking statements at the end of the time step.
8. Variable And Signal Which Will Be Updated First?
Signals
9. What Is a Sensitivity List?
The sensitivity list indicates that when a change occurs to any one of the
elements in the list change, the begin…end statement inside that always block
will get executed.
10. In A Pure Combinational Circuit, Is It Necessary To Mention All The
Inputs In Sensitivity Disk? If Yes, Why?
Yes, in a pure combinational circuit, it is necessary to mention all the inputs in the
sensitivity disk; otherwise, it will result in pre and post-synthesis mismatch.
12. Difference Between Verilog And Vhdl?
Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same
system file, may be separately compiled if so desired. However, it is good
design practice to keep each design unit in it’s own system file in which case
separate compilation should not be an issue.
Verilog. The Verilog language is still rooted in it’s native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the
original nature of the language. As a result care must be taken with both the
compilation order of code written in a single file and the compilation order of
multiple files. Simulation results can change by simply changing the order of
compilation.
Data types
VHDL. A multitude of language or user defined data types can be used. This may
mean dedicated conversion functions are needed to convert objects from one
type to another. The choice of which data types to use should be considered
wisely, especially enumerated (abstract) data types. This will make models
easier to write, clearer to read and avoid unnecessary conversion functions that
can clutter the code. VHDL may be preferred because it allows a multitude of
language or user defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and
very much geared towards modeling hardware structure as opposed to abstract
hardware modeling. Unlike VHDL, all data types used in a Verilog model are
defined by the Verilog language and not by the user. There are net data types,
for example wire, and a register data type called reg. A model with a signal
whose type is one of the net data types has a corresponding electrical wire in
the implied modeled circuit. Objects, that is signals, of type reg hold their value
over simulation delta cycles and should not be confused with the modeling of a
hardware register. Verilog may be preferred because of it’s simplicity.
Design reusability
VHDL. Procedures and functions may be placed in a package so that they are
available to any design unit that wishes to use them.
Verilog. There is no concept of packages in Verilog. Functions and procedures
used within a model must be defined in the module. To make functions and
procedures generally accessible from different module statements, the functions
and procedures must be placed in a separate system file and included using the
`include compiler directive.
13. Can You Tell Me Some Of System Tasks And Their Purpose?
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
The most useful of these is $display. This can be used for displaying strings,
expression or values of variables.
Here are some examples of usage.
$display(“Hello oni”);
— output: Hello oni
$display($time) // current simulation time.
— output: 460
counter = 4’b10;
$display(” The count is %b”, counter);
— output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it
in interactive mode where the user can enter commands; $finish exits the
simulator back to the operating system
14. Can You List Out Some Of Enhancements In Verilog 2001?
In an earlier version of Verilog, we used ‘or’ to specify more than one element in
the sensitivity list. In Verilog 2001, we can use commas, as shown in the
example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)
Verilog 2001 allows us to use the stars in a sensitive list instead of listing all the
variables in the RHS of combo logic. This removes typo mistakes and thus
avoids simulation and synthesis mismatches, Verilog 2001 allows port direction
and data type in the port list of modules, as shown in the example below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
15. Write A Verilog Code For Synchronous And Asynchronous Reset?
Synchronous reset, synchronous means clock dependent so reset must not be
present in sensitivity disk
eg: always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous means clock-independent, so reset must be present in the
sensitivity list.
Eg: Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end
16. What Is Pli?why Is It Used?
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface
Verilog programs with programs written in C language. It also provides
mechanism to access internal databases of the simulator from the C program.
PLI is used for implementing system calls which would have been hard to do
otherwise (or impossible) using Verilog syntax. Or, in other words, you can take
advantage of both the paradigms – parallel and hardware related features of
Verilog and sequential flow of C – using PLI.
17. There Is A Triangle And On It There Are 3 Ants One On Each Corner
And Are Free To Move Along Sides Of Triangle What Is Probability That
They Will Collide?
Ants can move only along edges of triangle in either of direction, let’s say one is
represented by 1 and another by 0, since there are 3 sides eight combinations
are possible, when all ants are going in same direction they won’t collide that is
111 or 000 so probability of not collision is 2/8=1/4 or collision probability is
6/8=3/4
18. How To Write Fsm Is Verilog?
there r mainly 4 ways 2 write fsm code
1.
1.
1. using 1 process where all input decoder, present state, and
output decoder r combine in one process.
2. using 2 process where all comb ckt and sequential ckt
separated in different process
3. using 2 process where input decoder and persent state r
combine and output decoder seperated in other process
4. using 3 process where all three, input decoder, present state
and output decoder r separated in 3 process.
19. What Is Difference Between Freeze Deposit And Force?
$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is
the register or net to be changed; value is the new value for the register or net.
The value remains until there is a subsequent driver transaction or another
$deposit task for the same register or net. This system task operates identically
to the ModelSim force -deposit command.
The force command has -freeze, -drive, and -deposit options. When none of these
is specified, then -freeze is assumed for unresolved signals and -drive is
assumed for resolved signals. This is designed to provide compatibility with
force files. But if you prefer -freeze as the default for both resolved and
unresolved signals.
20. Will Case Infer Priority Register If Yes How Give An Example?
yes case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2’b00: r = a;
2’b01: r = b;
endcase
end
21. Given The Following Verilog Code, What Value Of “a” Is Displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
This is a tricky one! Verilog scheduling semantics basically imply a four-level deep
queue for the current simulation time:
1. Active Events (blocking statements)
2. Inactive Events (#0 delays, etc)
3. Non-Blocking Assign Updates (non-blocking statements)
4. Monitor Events ($display, $monitor, etc).
Since the “a = 0” is an active event, it is scheduled into the 1st “queue”.
The “a <= 1” is a non-blocking event, so it’s placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the
active queue are completed this sim cycle, so the “a = 0” happens, and then
the display shows a = 0. If we were to look at the value of a in the next sim
cycle, it would show 1.
22. What Is The Difference Between The Following Two Lines Of Verilog
Code?
#5 a = b;
a = #5 b;
#5 a = b;
Wait five time units before doing the action for “a = b;”.
a = #5 b; The value of b is calculated and stored in an internal temp register,After
five time units, assign this stored value to a.
23. What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?
‘timescale directive is a compiler directive.It is used to measure simulation time
or delay time. Usage :`timescale / reference_time_unit : Specifies the unit of
 measurement for times and delays. time_precision: specifies the precision to
which the delays are rounded off.
24. What Is The Difference Between === And == ?
output of “==” can be 1, 0 or X.
output of “===” can only be 0 or 1.
When you are comparing 2 nos using “==” and if one/both the numbers have one
or more bits as “x” then the output would be “X” . But if use “===” outpout
would be 0 or 1.
e.g A = 3’b1x0
B = 3’b10x
A == B will give X as output.
A === B will give 0 as output.
“==” is used for comparison of only 1’s and 0’s .It can’t compare Xs. If any bit of
the input is X output will be X
“===” is used for comparison of X also.
25. How To Generate Sine Wav Using Verilog Coding Style?
The easiest and efficient way to generate sine wave is using CORDIC Algorithm.
26. What Is The Difference Between Wire And Reg?
(wire,tri)Physical connection between structural elements. Value assigned by a
continuous assignment or a gate output. Register type: (reg, integer, time, real,
real time) represents abstract data storage element. Assigned values only within
an always statement or an initial statement. The main difference between wire
and reg is wire cannot hold (store) the value when there no connection between
a and b like a->b, if there is no connection in a and b, wire loose value. But reg
can hold the value even if there in no connection. Default values:wire is Z,reg is
x.
27. How Do You Implement The Bi-directional Ports In Verilog Hdl?
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8’bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule
28. What Is Verilog Case (1) ?
wire [3:0] x;
always @(…) begin
case (1’b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one that
matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the
statement that will get executed (or selected by the logic).
29. Why Is It That “if (2’b01 & 2’b10)…” Doesn’t Run The True Case?
This is a popular coding error. You used the bit wise AND operator (&) where you
meant to use the logical AND operator (&&).
30. What Are Different Types Of Verilog Simulators ?
There are mainly two types of simulators available.
 Event Driven

 Cycle Based

Event-based Simulator:
This Digital Logic Simulation method sacrifices performance for rich
functionality: every active signal is calculated for every device it propagates
through during a clock cycle. Full Event-based simulators support 4-28 states;
simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full
timing calculations for all devices; and the full HDL standard. Event-based
simulators are like a Swiss Army knife with many different features but none are
particularly fast.
Cycle Based Simulator:
This is a Digital Logic Simulation method that eliminates unnecessary calculations
to achieve huge performance gains in verifying Boolean logic:
1. Results are only examined at the end of every clock cycle; and
2. The digital logic is the only part of the design simulated (no timing
calculations). By limiting the calculations, Cycle based Simulators can provide
huge increases in performance over conventional Event-based simulators.
Cycle based simulators are more like a high speed electric carving knife in
comparison because they focus on a subset of the biggest problem: logic
verification.
Cycle based simulators are almost invariably used along with Static Timing
verifier to compensate for the lost timing information coverage.

Difficult level questions

1. Why always block is not used inside a program block?
The program block is generally used to develop a test case that initiates a
stimulus and then it should end. But the ‘always’ block does not have any
provision to end by itself. Thus, we can not have a program block. Even if you
try to do so, a compilation error is expected.
For a need basic, we can use the ‘forever’ loop as a work-around with a ‘break’
statement to terminate the loop as per requirement.
2. What is FIFO? What are underflow and overflow conditions in FIFO?
Write Verilog code for the design.
FIFO stands for first in first out which means that the first element enters into the
buffer and comes out first.
Underflow: When an attempt is made to read data from an empty FIFO, it is
called an underflow. The design should have an ‘empty’ flag to avoid getting
invalid values
Overflow: When an attempt is made to write data into the already full FIFO, it is
called an overflow. The design should have a ‘full’ flag to avoid losing the data
sent from the previous module.
Refer verilog implementation of FIFO to explain working read and write pointers to
determine underflow and overflow conditions: Synchronous FIFO
3. What are all different applications of FIFO?
Buffers: To hold data immediately till we get acknowledgment whether previous
data is processed by a design or not.
Clock domain crossing: To exchange data between two systems that work on
different clock frequencies
Ordering requirement in design: FIFO helps to process the data in the
required order which ensures data is not overridden mistakenly. This is very
helpful in microprocessors, and GPU designs, etc.
Pipeline Stages: FIFO makes sure the data flows in different pipeline stages to
process multiple instructions concurrently.
4. What will happen if there is no else part in if-else?
In such a case, the missing ‘else’ (i.e. valid = 0 in the below case) infers to latch
in synthesis.
Example:
always@(*) begin
if(en) begin
data <= 8‘hFF;
end
end
5. Swap register content with and without using an extra register.
Without using an extra register:
always @(posedge clk) begin
m <= n;
n <= m;
end
Copy
Using an extra register (in case the interviewer asks):
Here, temp is an extra register used.
always @(posedge clk) begin
temp = n;
n = m;
m = temp;
end
Copy
6. What is infer latch means? How can you avoid it?
Infer latch means creating a feedback loop from the output back to the input due
to missing if-else condition or missing ‘default’ in a ‘case’ statement.
Infer latch indicates that the design might not be implemented as intended and
can result in race conditions and timing issues.
How to avoid it?
1. Always use all branches in the ‘if’ and ‘case’ statements.
2. Use default in the ‘case’ statement.
3. Have a proper code review.
4. Use lint tools, and logical-equivalence-check tools
7. How can you define strength in Verilog
Refer strength in Verilog
8. What is parameter overriding in Verilog?
Verilog parameter is used to pass a constant to the module when it is
instantiated. The parameter value can not be changed at run time.
There are two ways to override the parameters in Verilog
1. During module instantiation
module param_example #(parameter DATA_WIDTH = 8, ID_WIDTH = 32) (data,
id);
param_example #(4, 16) p2(.data(3), .id(2));
Copy
2. Using defparam
defparam p4.DATA_WIDTH = 10;
defparam p4.ID_WIDTH = 16;
Copy
9. Write a Verilog code for 5:1 MUX
5:1 MUX selects one out of 5 signals based on 3-bit select input and forwards it to
single-bit output.
module mux_5_1 (input [4:0] i_data, [2:0] sel, output reg out);
always@(*) begin
case(sel)
5'h0: out = i_data[0];
5'h1: out = i_data[1];
5'h2: out = i_data[2];
5'h3: out = i_data[3];
default: out = i_data[4];
endcase
end
endmodule
Copy
10. Can you talk about the Verilog event scheduler?
The Verilog scheduling semantics is used to describe the Verilog language
element’s behavior and their interaction with each other. This interaction is
described for event execution and its scheduling. Verilog is like a parallel
programming language in terms of blocks or process executions. Hence, the
user should know the guaranteed or indeterminate execution order while using
it.

11. What is `timescale? What does `timescale 1 ns/ 1 ps in a Verilog

code?
It is a ‘compile directive’ and is used for the measurement of simulation time and
delay. Refer: `timescale
12. What will be the output of m, n, o if c is the clock?
logic m = c;
reg n = c;
wire o = c;
Copy
Since clock c needs to be generated, it has to be of reg type. If we do direct
assignment as above, then m and n will have default values as x and wire o will
be the same as how clock is driven.
But if we do declaration and assignment in the ‘always’ block then m and n can
be driven same as a clock, but ‘o = c’ assignment can not be possible inside
‘always’ block as the ‘o’ variable is a wire type.

How do u avoid setup and hold violation ? (Quora)

Link to study STA:
https://www.vlsi-expert.com/2014/01/10-ways-to-fix-setup-and-hold-violation.html
Setup Time: and Hold Time: If the data or signal changes just before and after
the active edge of the clock respectively then we say that setup time/ hold time
has been violated.
Causes for Setup Time: Setup violations can happen as a result of slow
conditions (slow process, high temperature) leading to signals arriving too late
in the clock period.
Strategy to Fix Setup Time: Reduce Delay.
*As a RTL Design Engineer*:
1. If the RTL code is a FSM , change the states of a FSM to one hot encode or
grey code. If only one bit is changing at a time, it is a good chance that it would
be faster and less delay.
2. Prefer to use case statement over if else. Case statements and if else
statements would have the same functionality but synthesis captures them
differently. If there are multiple branch conditions, case statements (which is a
mux) would be faster than synthesized if else (which would be priority encoder).
3. Achieve Parallelism in RTL Serial Codes elongate the critical path and that
is BAD. If we can split large serial operation in to multiple parallel operations
then it is simple to meet timing of small individual units.
*As a Physical Design Engineer*:
1. Make use of macros Each industry I believe would be having specific
macros available. These are usually best optimized cells.
2. Try to make use of libraries derived from NAND logic. Since , NAND and
NOR are universal gates and NAND being faster than NOR they could be utilized
to reduce delay. For example: if NAND is followed by a latch, simply use latch-
NAND driver.
3. Increase Wire Thickness (reduces resistance) and increase the spacing
between wires (decreases coupling capacitance).
4. Use Cells with lower Threshold Voltages: Cells with lower threshold voltage
have lesser transition times which makes the propagation of logic faster.
5. Restructuring/Re-timing would be the best way to optimize the logic.
Based upon the placement of data path logic cells, you can decide either to
combine simple logic gates into a complex gate, or split a multi-stage cell into
simpler logic gates.
6. A cell with better drive strength can charge the load capacitance quickly,
resulting in lesser propagation delay. So make sure you cell has better drive
strength. (Traditionally , I believe larger cells should be having more driving
strength).
7. For a critical path with a capture flop and a launch flop , try to ensure that
the clock at the capture flop comes late or the clock at the launch flop comes
early. This will give some extra timing and will be able to relax any violations we
would be facing.
Alternative Explanation (for point 7th) : Positive skew helps improve the setup
slack. So, to fix setup violation, we may either choose to increase the clock
latency of capturing flip-flop, or decrease the clock latency of launching flip-flop.
I am happy to provide diagrammatic explanations as well, if you are interested in
explanation with diagrams do comment it.
Causes for Hold Time Violations: Hold violations can happen as a result of fast
conditions (fast process, low temperature) leading to signals arriving too early in
the clock period.
Strategy to Fix Hold Time:
*As a Physical Design Engineer*
1. Insert buffers. The timing path where hold violation is occurring, if the
delay is increased due to these buffers, then it shall ultimately lead to positive
slack thereby improving the chances of hold time being met.
2. Use data-path cells with higher threshold voltages: If you have multiple
varieties of cells with variable threshold voltages, then the cells with higher
threshold voltage will have higher transition times. This reduces the chances of
the hold time being violated.
3. Lock up Latches: If we some how try to separate the launching edge and
capturing edge by a phase then it will relax the timing path and improves the
chances of hold time being met. [Image shown at the last]
4. A positive skew degrades hold timing and a negative skew aids hold
timing. So, if a data-path is violating, we can either decrease the latency of
capturing flip-flop or increase the clock latency of launching flip-flop.
Alternative explanation for last point: For a capture and launch flop, if the clock at
the launch flop is made to arrive late or the clock at the capture flop is made to
arrive early then the chances of hold time being violated is reduced.
Image shown for Lockup Latches:
Answer 2
First of all, you have to use worst case specifications for all components at the
worst case of power supply voltage and temperature. You can cheat, but it leads
to unreliable designs. You have to pin down suppliers and actually qualify lots of
parts as well.
To get accurate figures you also need to account for net loading, net capacitance,
and speed of light delays. Loading will slow down the transitions, and delay the
time at which the input voltage to a gate crosses Vil or Vih. Buy good CAD tools.
You can even run SPICE on a few bad nets.
You also have to know the worst case clock jitter at every register.
For setup times, sort all paths by slowest to fastest. At some clock speed, there
will be no setup violations. If that is fast enough, declare victory and set the
clock a bit slower to have some margin.
If it isn’t fast enough, fix the slowest path. There are lots of techniques.
 Eliminate logic levels by combining levels and using wider gates
 Reduce loading by making multiple copies of signals

 Change the board layout to make the critical paths shorter

 Use stronger drivers to charge capacitance more quickly.

 Paradoxically, put the critial load at the end of the net (for TTL and CMOS) so
that you get incident wave switching. For ECL or terminated lines, put the
critical load first.
 Use higher power or faster parts in critical spots. Ie STTL instead of LSTTL.

 Add another pipeline stage. You can make the clock faster and the extra latency
may not matter.
Hold time violations are unusual.
 Reduce clock jitter. For example, drive both ends of a fast-path with the same
copy of the clock.
 Place the load on a too-fast path farther away. Add extra length to the traces.

 Add do-nothing buffers to the too-fast path, like two inverters.

 Do not add RC filters. That is just tacky.

What is Setup and Hold Time in an FPGA?

Setup time and Hold time are important concepts to understand for every digital
designer. This article explains what setup and hold times are and how they are
used inside of an FPGA. This article assumes that the reader has at least a basic
understanding of what a Flip-Flop is and how propagation delay affects designs.
 As a refresher, propagation delay is
the amount of time it takes for signals to pass between two Flip-Flops. As a
signal travels down a wire, it can change from a 0->1 or 1->0. An input to a Flip-
Flop needs to be stable (not changing) in order for an FPGA design to work
properly. The input must be stable for some small amount of time prior to being
sampled by the clock. This amount of time is called setup time. Setup time is
the amount of time required for the input to a Flip-Flop to be
stable before a clock edge. Hold time is similar to setup time, but it deals
with events after a clock edge occurs. Hold time is the minimum amount of
time required for the input to a Flip-Flop to be stable after a clock
edge.
In the figure, the green area represents the t su or Setup Time. The blue area
represents the th or Hold Time. In these areas, the data into the Flip-Flop must
be a stable 0 or a 1 or bad things will happen…
How does Setup and Hold time Relate to Propagation Delay and Clock
Frequency?
Setup time, hold time, and propagation delay all affect your FPGA design timing.
The FPGA tools will check to make sure that your design meets timing, which
means that the clock is not running faster than the logic allows. The minimum
amount of time allowed for your FPGA clock (its Period, which is represented
by T) can be calculated. From this you can find the clock’s frequency, as
frequency is the inverse of period (F=1/T). It is as follows:
tclk (min) = tsu + th + tp
Generally in your FPGA design, tsu and th are fixed for your Flip-Flops, so the only
variable that you have control over is t p or the Propagation Delay. This delay
represents how much stuff you’re trying to accomplish in one clock cycle. The
more stuff you try to do, the longer t p will be, and the higher tclk (min) will be,
which means that you will not be able to clock your FPGA design as quickly. This
is the fundamental trade-off of FPGA designs. You are trading off how much stuff
you can do in one clock cycle for the frequency of your clock. The two are
inversely related… there’s no such thing as a free lunch!
What Happens if Setup and Hold Times Are Violated?
If your design has setup or hold time violations, the Flip-Flop output is not
guaranteed to be stable. It could be zero, it could be one, it could be somewhere
in the middle, it’s not known. This is called metastability. Metastability inside
of an FPGA is not desirable, it can cause your FPGA to behave strangely. The
physics behind metastability are interesting, you can read more about
metastability here.
The main way that an FPGA designer finds out if they have violated setup or hold
times is when running the FPGA through Place and Route. Place and Route is
what happens when you take your VHDL or Verilog code and put it onto an
FPGA. As a part of this process, the FPGA tools will take your design and run
a timing analysis. It is in this timing analysis that you will see any timing errors,
which are really just setup or hold time violations. How to fix these errors is
beyond the scope of this article, but read the article on Propagation Delay to see
how these timing errors can be fixed.
In conclusion, setup time and hold time is an important concept for an
FPGA designer to understand. If these times are violated, the FPGA will
not perform as expected!
Quiz Questions
Q. If a Flip-Flop has a 1 nanosecond (ns) setup time, what is the minimum amount
of time that is required for the data to be stable prior to the clock?
A. 1 ns. This is the definition of setup time
Q. If two Flip-Flops have 1 ns setup time, 1 ns hold time, and 8 ns of propagation
delay, what is the maximum frequency that this clock can run?
A. tclk (min) = tsu + th + tp. So tclk (min) = 1 ns + 1 ns + 8 ns = 10 ns. Remember that
F=1/T, where T = 10 ns. F = 100 MHz.
Q. If you have a 50 MHz clock, 1 ns setup time, and 2 ns hold time, what will your
design allow for its maximum propagation delay between two flip-flops?
A. tclk (min) = tsu + th + tp. Since F=1/T, tclk = 20 ns. So 20 ns = 1 ns + 2 ns + t p. tp =
17 ns
Q. If you have a situation where you have a 200 MHz clock and you have timing
errors after running through Place and Route, what might you be able to do to
fix this?
A. Timing errors are caused when you violate the equation t clk (min) = tsu + th + tp.
Since setup time, hold time, and clock frequency are fixed, the only variable you
can to play with is the propagation time. The simplest way to lower your
propagation time is to cut down on the amount of stuff that you are trying to
accomplish in 1 clock cycle. Divide your logic from 1 clock cycle into 2 clock
cycles or more. For more information on this, read the article about propagation
delay.