Analysis and design of

Combinational logic :
Module :2
Decoders:
• Decoders: are a class of combinational logic circuits that convert a set
of input variables representing a code into a set of output variables
representing a different code.
• The relation between input and output can be expressed using truth
table . Encoded information is presented as n –inputs producing 2n
outputs, the 2n outputs can range from 0- 2n – 1.
• Several decoder IC’s are commercially available in market.
• There are 2 types of decoders
• The one that follow n:2n Ratio.
• The other that does not like 4:10 line decoder where few lines are truncated
as they will never be generated.
Applications:
• An important part of the system which selects the cells to be read
from and written into is the decoder.
–Accepts a value and decodes it
•Output corresponds to value of n inputs
•It also is called many-to-one decoder, a decoder matrix or simply a
decoder.
A decoder consists of:
Inputs (n)
Outputs (2n , numbered from 0 – (2n - 1))
Selectors / Enable (active high or active low)
• The decoder has the characteristic that for each of the possible 2n binary input
numbers which can be taken by the n input cells, the matrix will have a
unique one of its 2n output lines selected.
• Example:
Enable Input:
• Many devices have an additional enable input, which is used to “activate”
or “deactivate” the device.
•For a decoder,
–EN=1 activates the decoder, so it behaves as specified earlier. Exactly one of the
outputs will be 1.
–EN=0 “deactivates” the decoder. By convention, that means all of the decoder’s
outputs are 0.
• We can include this additional input in the decoder’s truth table:
IC Decoders: IC 74xx139(MSI)(Dual 2:4 decoder IC)
IC 74xx138(MSI)( 3:8 decoder IC):
To realize a Boolean function using Decoders:
An n : 2n decoder with active high input is an minterm generator, an decoder with active low output is a
maxterm generator
• Implement the following functions using a 3:8 decoder :
f1(x2,x1,x0)=∑m(1,2,4,5) and f2(x2,x1,x0)=∑(1,5,7).(realizing minterms)
Implement the following functions
using a 3:8 decoder :
f1(x2,x1,x0)=∑m(0,1,3,4,5,6) and
f2(x2,x1,x0)=∑(1,2,3,4,6).
Using Complementary expression to
minimize the connections.
Realize f1(x2,x1,x0)=∏M(0,1,3,5) and
f2(x2,x1,x0)=∏M(1,3,6,7)(Maxterm realization).

• Maxterm realization is counting zeros hence while using OR gate the minterms are connected, and vice
versa.
Realize the pair of Maxterm canonical expressions:
f1(x2,x1,x0)=∏M(0,3,5) and
f2(x2,x1,x0)=∏M(2,3,4)
f1(x2,x1,x0)=∏M(0,1,3,4,7) and
f2(x2,x1,x0)=∏M(1,2,3,4,5,6)
Realize the following Boolean function using
decoder with active low output.
f1(x2,x1,x0)=∑m(0,2,6,7) and
f2(x2,x1,x0)=∏M(3,5,6,7)
Sl No Type of Type of Type of gate
output equation used
1 Active high ∑m OR gate (SOP)
2 Active high ∏M NOR gate (POS)
3 Active low ∏M AND gate (POS)
4 Active Low ∑m Nand Gate (SOP)
• Realize X=f(a,b,c)=∑m(0,3,5,6,7) using IC 74xx138
 Application using enable
inputs:
• Its majorly used to construct a
larger decoder using a network of
smaller decoder.
• Like one 4:16 decoder using 2:4
decoder .
Realize a 4:16
decoder using
74xx138 IC.
Realize a 5:32 decoder
using a 2:4 decoder and
four 3:8 decoder.
Realize a four-
variable multiple
output function
using 74xx138
decoder IC.
BCD Decoder:
IC 74xx47 BCD to 7-Segment decoder:
 Encoder:
• They act inversely to Decoders, they
also have multiple inputs and
outputs like decoder, but in reverse
order that is 2n : n. n output and 2n
inputs.
• They also provide for the conversion
of binary information from one
form to another.
• A logic “1” on one of its input line
causes the corresponding binary
code to appear at the output lines.
• If we can assume at any time only
one input is asserted then the 2n : n
line encoder is simply a collection of
OR gates.
IC 74xx147 a, 10-line to BCD encoder
(MSI):
Application of 74xx147(Key pad interface):
8:3 line Encoder IC 74xx148:
 Application of IC 74xx148(Control system priority
Encoder):
E7:Highest priority-fire alarm.
E6:Next higher Priority-main power failure.
E5:Next higher Priority-System safety
Interlock1.
E4:Next higher Priority-System safety
Interlock2.
E3:Next higher Priority- Machine station 1
operator interlock.
E2:Next higher Priority- Machine station 2
operator interlock.
E1:Next higher Priority- Machine station 3
operator interlock.
E0:Next higher Priority- Machine station 4
operator interlock.
Digital Multiplexers(MUX):
• Mux are also called data selectors . The
basic function of the device is to pass the
data from one of its 2n data input lines
onto its single output line.
• There are 2n input lines and only one
output line i.e. 2n :1 order.
• Since there are 2n input lines to select
from, n- bits are needed to specify which
input lines to be selected.
• Typically an enable or a strobe line can
also be included in the device.
• There are many commercial Mux
available in market:
• 74xx153-dual 4:1 mux,
• 74xx151-8:1 mux,
• 74xx150- 16:1 mux.
A tree of 4:1
multiplexer to form
16:1 multiplexer:
A Multiplexer and Decoder/ Demultiplexer
arranged for information transmission or
Exchange:
IC 74xx151 8:1 Mux:
Four 4-bit data
sources multiplexed
to a single 4-bit
destination:
A four-bit Multiplexer
system using two
74xx153 IC:
 Using multiplexers as Boolean function
generators:
• U=f(w,x,y,z)=∑m(0,1,5,6,7,9,13,14)
yz
00 01 11 10
00 1 1 0 0
wx 01
0 1 1 1
11 1 0 1 0
10 0 1 0 0
A 32:1 mux using
four 8:1 mux and
a 2 to 4 line
decoder:
Realize the Boolean function
using 8:1 Mux:
F=f(x,y,z)=∑m(1,2,4,5,7)
Realize the following Boolean function using
the least number of IC’s:
• S=f(a,b,c,d,e)=∑m(8,9,10,11,13,15,17,19,21,23,24,25,26,27,29,31).
• 1) simplify the expression
• 2)write the simplified expression and then determine the number of
remaining variables.
• 3) draw the logic diagram and determine the number of SSI IC’s required to
realize the function two SSI IC’s are needed , with gates left over.
• 4)Determine the multiplexer size based on the number of remaining
variables.
Adders and subtractors:
Half adder:
Full Adder:
Half Subtractor:
D=A xor B xor B-in
B-out= X’Y+X’(B-in)+y(B-in)
Cascading full adders:
Carry Look Ahead Adder:
Where:
Cp(carry Propagate signal)=Xi+Yi;
Cg(carry generate)= Xi.Yi;
Binary comparator:
A B A EQ B A>B A<B
1- Bit Comparator: 0 0 1 0 0
• A EQ B= A’B’+AB = A XNOR B; 0 1 0 0 1
1 0 0 1 0
• A>B= AB’;
1 1 1 0 0
• A<B=A’B;
2-bit magnitude
comparator:
Basic iterative circuit model:
 4-bit Itterative Comparator:

Optimized circuit with 2-bit encoding and a decoder logic: