VISVESVARAYATECHNOLOGICAL UNIVERSITY

BELAGAVI- 590018, KARNATAK

ADVANCED VLSI MINI PROJECT REPORT

ON

“A High Performance Scan Flip-Flop Design for

Serial and Mixed Mode Scan Test”
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by

ABHILASH H 1SJ21EC001
CHETHAN R 1SJ21EC034
NITHESH KUMAR K 1SJ19EC111

Under the guidance of

Dr.Veena S
Assistant Professor
Dept. Of ECE, SJCIT

DEPARTMENT OFELECTRONICS AND COMMUNICATION

ENGINEERING
SJC INSTITUTE OFTECHNOLOGY
CHICKBALLAPUR-562 101
2024-2025
A High Performance Scan Flip-Flop Design for
Serial and Mixed Mode Scan Test
1. ABSTRACT

Serial scan architecture is widely accepted due to its ease of examination and high test
coverage. However, it comes with penalties like performance overhead, increased test
data volume, longer test times, and higher test power dissipation. To address these issues,
a new scan flip-flop design has been proposed that eliminates performance overhead by
removing the scan multiplexer from the functional path. This new design can be used
both as a serial scan cell and a Random Access Scan (RAS) cell, leading to significant
reductions in interconnect wire length, test time, and test data volume compared to
existing RAS and multiple serial scan implementations.

2. INTRODUCTION

Scan architecture is the only discrete Fourier transform access that can effectively analyse
an eminently convoluted architecture with very immense fault coverage. The objective of
scan architecture is to accomplish full controllability and observability of every flip-flop
in the architecture. In full scan architecture, each flip flop is replaced by a scan flip-flop.
A scan flip-flop is nothing but a muxed input master-slave based d type flip-flop.the scan
multiplexer has two inputs: Data Input (D) and ScanInput (SI). The input excerpt is
performed using a control signal called a Test Enable (TE). In functional mode, data input
is excerpted and the scan flip-flop functions as a legitimate flip flop. In test mode, scan
input is excerpted, and all the scan flip-flops connect in a serial fashion to form one or
more serial shift register(s). The serial shift register(s) is popularly known as scan
chain(s). All flip-flops of the scan chain are burdened with desired data by consecutive
application of the clock signal. A full scan design diminishes the sequential test obstacle
to combinational test obstacle. The serial scan is evidently not complimentary from snags.
There are a few innate penalties comrade with the serial scan. These penalties include:
performance overhead, test data volume, test power consumption, and test application
time. The performance overhead regarding serial scan is by cause of the scan multiplexer
[1], [2]. The scan multiplexer plunges into each clocked path and augments performance
penalty of roughly two gate delays. A circuit without scan design and with scan design is
shown in figure 1.1. As it is discernible in figure 1.1(a), the critical path of a sequential
circuit without scan insertion is determined by the protracted combinational path betwixt
two flip-flops. However, in a scan inserted sequential circuit the same critical path is
elongated by a scan multiplexer situated at the confine of the combinational path. The
scan design also augments an extra fan-out at the output of a flip-flop.

The critical path delay can reduce functional clock speed by 5% to 10%, making it
essential to eliminate the performance overhead of the scan multiplexer. Partial scan
design is one solution, where only some flip-flops in the Circuit-Under-Test (CUT) are
replaced with scan flip-flops, avoiding those in critical paths. This reduces the
performance penalty, test data volume, and test application time, though it may result in
lower fault coverage. Various techniques for partial scan design include testability
measures, structure-based approaches, and Automatic Test Pattern Generation (ATPG).
Each has its own advantages and challenges. Another approach to eliminating
performance penalties is using high-performance scan cell designs.

3. EXISTING SYSTEM
A conventional scan flip-flop is a master-slave latch based positive edge triggered muxed
input D type flip-flop. It uses transmission gates and inverters to form the master and
slave latches. A multiplexer at the input of the master latch selects between functional
input (D) and scan input (SI) based on the test control signal (TE). In test mode, when TE
is high, the scan input is connected to the master latch's input. The master latch then
propagates the value to the slave latch on the clock's rising edge. In functional mode,
when TE is low, the functional input is selected, and the flip-flop operates normally.
3.1 PROPOSED SYSTEM
The proposed scan flip-flop design eliminates the multiplexer at the master latch's input,
providing an independent path for loading test vector values into the master latch. It uses
a low-cost dynamic slave latch for test mode and operates as a traditional flip-flop in
functional mode. Extraneous gates added to form the test mode input path are not on the
functional path, ensuring no performance overhead during regular operation. The master
and slave latches are controlled by the functional clock signal (CP), while the test mode
input path is controlled by the test enable cum scan clock signal (SCK).
3.2 FUNCTIONAL MODE:
In functional mode, the proposed scan flip-flop works like a traditional flip-flop, with the
scan clock signal (SCK) held at a steady high level. This keeps transmission gates T5 and
T6 inactive, disconnecting the test mode input path. The master latch receives its input
from the functional data input D, and the slave latch is always transparent. When the
clock signal (CP) is low, the functional input D is loaded into the master latch. When CP
is high, the value propagates from the master latch to the slave latch and to the output Q
of the scan cell. The scan output (SO) toggles with changes in the master latch's state but
is not a concern in functional mode.
3.3 TEST MODE
In test mode, the functional clock CP is held at a constant high level, keeping
transmission gate T1 disabled and disconnecting the functional input D from the master
latch. The master latch receives input from the scan input SI through the scan clock SCK.
When SCK is low, gates T5 and T6 enable writing the SI value into the master latch. The
master latch retains its previous value as T2 remains enabled. When SCK goes high, gate
T7 enables, and the master latch drives the dynamic and functional slave latches,
propagating the test value to the scan output SO. When SCK is low again, T7 is disabled,
and the input parasitic capacitance of inverter i7 drives the next scan cell’s scan input SI.
The proposed scan flip-flop's parasitic capacitance discharge time influences the
minimum scan clock frequency, which depends on the input capacitance of inverter i7
and the charge leakage rate. The size of inverter i7 can be adjusted to optimize discharge
time. However, a low shift frequency is undesirable as it increases test time and cost. In
test mode, transmission gate T3 remains enabled, keeping the functional slave latch
transparent and causing the output (Q) to toggle with changes in the master latch's state.
The master latches in the scan chain receive inputs from preceding flip-flops' outputs,
except the first master latch, which gets its input from a primary pin. The dynamic slave
latch helps in shifting test vectors into the scan chain, and once loaded, the test vector is
launched via the functional slave latch.

4. RESULTS AND DISCUSSIONS

The conventional scan design operates in two modes: functional mode and test mode. In
test mode, when the Test Enable (TE) signal is high (1), the scan input (SI) is selected and
connected to the master latch's input. When the clock signal (CP) is low (0), the value of
SI propagates to the master latch. In functional mode, when TE is set to low (0), the
functional input (D) is selected, and the circuit operates accordingly. The output of this
design is illustrated in Figure 5.4.
As a conventional design, the newly designed proposed system also operates at two
different modes. They are the functional mode and the test mode. Here, in functional
mode, when a scan clock signal (SCK)is kept at constant logic high (1) level, the Clock
Pulse (CP) turns to low (0). Therefore, S0 will be the output. Also, in test mode, when
aScan Clock signal (SCK)is kept at constant logic low (0) level and Clock Pulse (CP)
turns to high (1). Therefore, Q will be the output.

The function of the proposed scan flip-flop is discussed above and its output is shown
above in figure 5.5. The area and delay of the proposed scan flip-flop is shown below in
the figure 5.6.
5. CONCLUSION AND FUTURE ENHANCEMENTS
We have contemplated a scan flip-flop design which eradicates the performance penalty
of the serial scan by dwindling scan multiplexer from the functional path. The new scan
flip-flop is adept of employing all conventional tests and fully acquiesces with the
conventional industry design and test flow. Additionally, the proposed scan flip-flop can
be used both as a serial scan cell as well as a RAS cell, in the mixed mode scan test. The
mixed mode scan design enforced with proposed scan flip-flop displays a promising
reduction in interconnect wire length, test data volume, and test application time.