Module 3 (BKM) - Arithmetic
Module 3 (BKM) - Arithmetic
2
Algorithm for Addition of signed magnitude
numbers
• When the signs of A and B are identical, add the two
magnitudes and attach the sign of A to the result.
• When the signs of A and B are different, compare the
magnitudes and subtract the smaller number from the
larger.
• Choose the sign of the result to be the same as A if A > B or the
complement of the sign of A if A < B.
• If the two magnitudes are equal, subtract B from A and
make the sign of the result positive.
Algorithm for Subtraction of signed magnitude
numbers
• When the signs of A and B are different, add the two
magnitudes and attach the sign of A to the result.
• When the signs of A and B are same, compare the
magnitudes and subtract the smaller number from the
larger.
• Choose the sign of the result to be the same as A if A > B or the
complement of the sign of A if A < B.
• If the two magnitudes are equal, subtract B from A and
make the sign of the result positive.
Hardware Implementation
Basic components of Hardware
Implementation
• It needs two registers to hold the magnitude of two numbers,
say A and B.
• As and Bs are two flip-flops to hold the corresponding signs.
• The result may be transferred to a third register or may be
accumulated in A and As.
• A+B is performed with the help of parallel adder.
• A-B is performed by adding the 2’s complement of B to A.
• A 2’s complement subtractor and comparator can be
implemented by using a complementer.
• The output carry is transferred to flip-flop E, which determines
the relative magnitude of two numbers.
• The AVF (Add OverFlow) flip-flop holds the overflow bit during
A+B.
Hardware Implementation Explanation
• The addition A+B is done through the parallel adder.
• The sum S output of the adder is applied to the input of A
register.
• The complementer provides an output of B or the complement
of B depending on the mode control M.
• The complementer consists of XOR gates and the parallel
adder consists of full adder circuits.
• The M signal is also applied to the input carry of the adder.
• When M=0, the output of B is transferred to the adder, the
input carry is 0, and the output of the adder is equal to the
sum A+B.
• When M=1, the 1’s complement of B is applied to the adder,
the input carry is 1, and the output S=A+B’+1 (That is the 2’s
complement of B subtracted from A)
Flowchart of
Addition/Subtraction
Hardware Algorithm
• The XOR decides
whether the signs of A
and B are identical or
not.
• If the AsBs=0, then the
signs are identical and
vice versa.
• For add operation,
identical signs means
the magnitudes to be
added.
• For subtract operation,
different sign means the
magnitudes to be
added.
Flowchart of
Addition/Subtraction
Hardware Algorithm-
Working
• The magnitudes are
added with a
microoperation
EA=A+B, where EA
is a register that
combines E and A.
• The carry in E after
the addition
constitutes an
overflow if it is
equal to 1.
• The value of E is
transferred into the
AVF.
Flowchart of
Addition/Subtraction
Hardware Algorithm-
Working
• The two magnitudes
are subtracted if the
signs are different
for an add operation
or identical for a
subtract operation.
• The subtraction is
done by adding 2’s
complement of B to
A.
• No overflow occurs
if the numbers are
subtracted. So AVF is
cleared to 0.
Flowchart of
Addition/Subtraction
Hardware Algorithm-
Working
• If E=1, it indicates A>=B
and the number in A is the
correct result if A≠0.
• If E=0, it indicates A<B and
2’s complement of A is
done.
• Since A<B, the sign of the
result is the complement
of the original sign of A.
• Therefore, As is
complemented to obtain
the correct sign.
• Finally, A and As give the
Addition/subtraction of signed numbers
xi yi Carry-in ci Sumsi Carry-outci +1
At the ith stage:
0 0 0 0 0 Input:
0 0 1 1 0 ci is the carry-in
0 1 0 1 0
0 1 1 0 1
Output:
1 0 0 1 0 si is the sum
1 0 1 0 1 ci+1 carry-out to (i+1)st
1 1 0 0 1
1 1 1 1 1 state
si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i yi ci
ci +1 = yi ci + xi ci + xi yi
Example:
X 7 0 1 1 1 Carry-out xi Carry-in
+Y = +6 = + 00 1 1 1 1 0 0 0 yi
ci+1 ci
Z 13 1 1 0 1 si
ci + 1 Full adder ci
(FA)
s
i
Full Adder (FA): Symbol for the complete circuit for a single stage of
addition.
n-bit adder
• Cascade n full adder (FA) blocks to form a n-bit adder.
• Carries propagate or ripple through this cascade,
hence called bit ripple carry adder.
x y x y x y
n- 1 n- 1 1 1 0 0
c c
n- 1 1
c FA FA FA c
n 0
s s s
n- 1 1 0
c
n-bit n-bit n n-bit
c c
kn adder adder adder 0
s s s s s s
kn - 1 (k - 1 ) n 2n - 1 n n- 1 0
n-bit subtractor
•Recall X – Y is equivalent to adding 2’s complement of Y to X.
•2’s complement is equivalent to 1’s complement + 1.
•X – Y = X + Y + 1
x y x y x y
n- 1 n- 1 1 1 0 0
c c
n- 1 1
c
n FA FA FA 1
s s s
n- 1 1 0
x x x
n- 1 1 0
c n-bit adder
n c
0
s s s
n- 1 1 0
Overflow cn cn 1
Computing the Add time
s0
Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
i
yi
Computing the Add time (contd..)
Cascade of 4 Full Adders, or a 4-bit adder
x3 y3 x2 y2 x1 y1 x0 y0
FA FA FA FA c0
c4 c3 c2 c1
s3 s2 s1 s0
4-bit
c4
B cell
c
3
B cell
c
2
B cell
c
1
B cell . c
0 carry-lookahead
adder
s s s s
3 2 1 0
G3 P3 G2 P2 G P G P
1 1 0 0
Carry-lookahead logic
xi yi
. .
. c
i
B-cell for a single stage
B cell
Gi P i
si
Carry-lookahead Adder(contd..)
• Performing n-bit addition in 4 gate delays independent of n is
good only theoretically because of fan-in constraints.
• Last AND gate and OR gate require a fan-in of (n+1) for a n-bit
adder.
• For a 4-bit adder (n=4) fan-in of 5 is required.
• Practical limit for most gates.
• In order to add operands longer than 4 bits, we can cascade
4-bit Carry-Lookahead adders.
• Cascade of Carry-Lookahead adders is called Blocked Carry-
Lookahead adder.
Blocked Carry-Lookahead adder
Carry-out from a 4-bit block can be given as:
c16 G3I P3I G2I P3I P2I G1I P3I P2I P10G0I P3I P2I P10P00c0
Blocked Carry-Lookahead adder
x15-12 y15-12 x11-8 y11-8 x7-4 y7-4 x3-0 y3-0
Carry-lookahead logic
Multiplicand
0 m3 0 m2 0 m1 0 m0
(PP0)
q0
0
PP1 p0
q1
0
PP2 p1
q2
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3
1 1 1 1 1 1 0 0 1 1
1 1 1 1 1 0 0 1 1
Sign extension is
shown in blue 0 0 0 0 0 0 0 0
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 0 1 1 1 0 0 0 1 ( - 143)
0 +1 -1 +1 0 - 1 0 +1 0 0 - 1 +1 - 1+1 0 - 1 0 0
Multiplier
Version of multiplicand(M)
selected by bit
Bit i Bit i -1
0 0 0 XM
0 1 +1 XM
1 0 1 XM
1 1 0 XM
Booth Multiplication Example
0 1 1 0 1 (+13) 01101
X 1 1 0 1 0 (- 6) 0-1+1-1 0
000 0000000
111 110011
000 01101
111 0011
000 000
111 0 1 1 0 0 1 0 (-78 )
Best case vs Worst case of Booth
Recoding
• Best case – a long string of 1’s
• Worst case – 0’s and 1’s are alternating
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Worst-case
multiplier
+1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1
1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0
Ordinary
multiplier
0 -1 0 0 +1 -1 +1 0 -1 +1 0 0 0 -1 0 0
0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1
Good
multiplier
0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1
Hardware Implementation of Booth
Algorithm
21 10101
13 274 1101 100010010
26 1101
14 10000
13 1101
1 1110
1101
1
Shift left
an an-1 a0 qn-1 q0
Dividend Q
A Quotient
Setting
0 mn-1 m0
Divisor M
Restoring Division
1. Initialize the register Q=dividend, M=divisor, A=0
Initialize count=n, where n=no. of bits of the dividend
and take M and Q as (n+1) bits by appending 0s
2. Repeat steps (3-7) while (count !=0)
3. Shift A and Q left one binary position
4. Subtract M from A, and place the answer back in A
5. If the sign of A is 1, set q0 to 0 and add M back to A
(restore A);
6. else set q0 to 1
7. count=count-1
8. Register Q gives the quotient and A gives the
remainder.
Restoring Division Example
Initially 0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0
Subtract 1 1 1 0 1 First cycle
Set q0 1 1 1 1 0
Restore 1 1
0 0 0 0 1 0 0 0 0
10 Shift 0 0 0 1 0 0 0 0
11 1000 Subtract 1 1 1 0 1
11 Set q0 1 1 1 1 1 Second cycle
Restore 1 1
10 0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Third cycle
Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1 Fourth cycle
Restore 1 1
0 0 0 1 0 0 0 1 0
Remainder Quotient
Nonrestoring Division
• It avoids restoring A after an unsuccessful subtraction.
1. Initialize the register Q=dividend, M=divisor, A=0 Initialize
count=n, where n=no. of bits of the dividend and take M and
Q as (n+1) bits by appending 0s
2. Shift A and Q left by one bit position
3. Repeat steps (a-e) while (count !=0)
a. If the sign of A is 0, subtract M from A
b. Else add M to A.
c. if the sign of A is 0, set q0 to 1
d. else set q0 to 0.
e. count=count-1
4. If the sign of A is 1, add M to A
5. Q gives the quotient and A gives the remainder.
Nonrestoring Division Example
Initially 0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0 First cycle
Subtract 1 1 1 0 1
Set q0 1 1 1 1 0 0 0 0 0
Shift 1 1 1 0 0 0 0 0
Add 0 0 0 1 1 Second cycle
Set q 1 1 1 1 1 0 0 0 0
0
Shift 1 1 1 1 0 0 0 0
1 1 1 1 1 Add 0 0 0 1 1 Third cycle
Restore
0 0 0 1 1 Set q 0 0 0 0 1 0 0 0 1
remainder 0
Add 0 0 0 1 0
Remainder Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourth cycle
Set q 1 1 1 1 1 0 0 1 0
0
Quotient
Floating-Point Numbers
and
Operations
Fixed Point vs Scientific notation
• In fixed point notation either the binary point is to the
immediate right or it is to the immediate left.
1 7 24
Multiplication:
3.1415 x 108 x 1.19 x 106 = (3.1415 x 1.19 ) x 10(8+6)
Division:
3.1415 x 108 / 1.19 x 106 = (3.1415 / 1.19 ) x 10(8-6)