Machine Instructions and

Programs
Dr. Bimal Kumar Meher
Associate Professor
Dept. of CSE
Topics to be covered
• Memory Location and addresses
• Big-endian and Little-endian representation
• Instruction Format
• Instruction sequencing
• Addressing modes
• Subroutines
• CISC vs RISC
Memory word
• A group of bits may represent a number,
n bits
character or instruction.
first word
• Memory of computer has million of cells second word
to store bits.
• Therefore, the memory is organized so •
•
that a group of n bits can be stored or •
retrieved in a single basic operation.
• Each group of n bits is referred to as a i th word

word of information and n is called the

word length. •
•
•
• Therefore, the memory is represented as
a collection of words. last word
32-bit word length example
32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location Addresses
• To retrieve information from memory, either for one word or one byte
(8-bit), addresses for each location are needed.
• A memory of k-bit address has 2k memory locations, namely 0 to 2k-1,
called memory space.
• Examples:
• If k = 4, then the memory addresses will be from 0 to 24-1(=15)
(Memory size = 16Byte).
• If k = 16, then the memory addresses will be from 0 to 216-1
(Memory size = 64KB).
• If k = 32, then the memory addresses will be from 0 to 232-1
(Memory size = ?).
• Note: 1KB=210; 1MB= 220; 1GB= 230; 1TB= 240 Bytes
Byte Addressable Memory
• The most practical way of assigning addresses is to assign successive
address values to successive byte locations in memory.
• This is called byte addressable memory.
• That means byte locations have addresses 0, 1, 2, …
• Therefore, if the word length of a machine is 32bits, then successive
words are located at byte addresses 0, 4, 8, … (where word length is
4bytes)
• What will be the word addresses if word length is 64bits?
Accessing numbers, characters, and strings
• A number usually occupies one word. It can be accessed in the
memory by specifying its word address.
• Similarly, individual characters can be accessed by their byte-
address.
• There are two ways to indicate the length of the string:
• 1) A special control character with the meaning "end of string" can be
used as the last character in the string.
• 2) A separate memory word location or register can contain a number
indicating the length of the string in bytes.
Big-Endian and Little-Endian Assignments
• Big-Endian: lower byte addresses are used for the most significant bytes of the word
• Little-Endian: lower byte addresses are used for the less significant bytes of the word
Word
address Byte address Byte address
0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4 word alignment: words

are said to be aligned in
• •
memory if they begin at
• • a byte address that is a
• •
multiple of the number
of bytes in a word.
k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Example: Big-Endian vs Little-Endian
• Big-Endian: lower byte addresses are used for the most significant bytes of the word
• Little-Endian: lower byte addresses are used for the less significant bytes of the word
Big-Endian
Address 0x100 0x101 0x102 0x103
0x01 0x02 0x03 0x04

Data
0x01020304

0x04 0x03 0x02 0x01

Address 0x100 0x101 0x102 0x103
Little-Endian
Memory Operation
• Two memory operations are: Load and Store
• The Load (or Read or Fetch) operation transfers a copy of the
contents of a specific memory-location to the processor.
• The memory contents remain unchanged.
• Registers can be used
• Steps for Load operation:
1. Processor sends the address of the desired location to the memory.
2. Processor issues READ signal to memory to fetch the data.
3. Memory reads the data stored at that address.
4. Memory sends the read data to the processor.
Memory Operation (contd…)
• The Store (or Write) operation transfers the information from the
register to the specified memory-location.
• This will overwrite the original contents of that memory-location.
• Registers can be used.
• Steps for Store operation are:
1. Processor sends the address of the memory-location where it wants
to store data.
2. Processor issues WRITE signal to memory to store the data.
3. Content of register MDR is written into the specified memory-
location.
Register Transfer Notation (RTN)
• The possible locations in which transfer of information occurs are:
• Memory locations
• Processor registers
• Registers in I/O device.
• So, we identify the location by a symbolic name, which stands for its
hardware binary address.
• Examples:
• Names for the addresses of memory locations: LOC, PLACE, A, VAR etc
• Names for processor registers: R0, R1 etc.
• Names for I/O registers: DATAIN, OUTSTATUS etc.
Register Transfer Notation (RTN)
• This is a type of notation which depicts the data transfer involving the
registers.
• In this type of notation:
• the right-hand side of the RTN expression is always denotes a value, and
• the left-hand side is the name of a location where the value is to be placed,
overwriting the old content.
• Note: The contents of a location are denoted by placing square
brackets around the name of the location.
• Example 1: R1 <- [LOC] means that the contents of memory location
LOC are transferred into processor register R1.
• Example 2: R3 <- [R1] + [R2] means the contents of registers R1 and
R2 are added and the sum is kept in R3.
Types of Instructions
• A program consists of a sequence of small steps like:
• Reading a character from the keyboard
• Adding two numbers
• Testing a condition
• Sending a character to the display screen
• And so on...
• Therefore, all the different operations of a computer are classified
into four types:
• Data transfer between the memory and processor registers
• Arithmetic and logical operations on data
• Program sequence and control
• I/O transfers
• Hence, there should be instructions for achieving those operations.
Assembly Language Notation
• This is a language used for representing machine instructions and
programs in a symbolic format.
• Example 1: An instruction that causes the transfer of data from
memory location LOC to register R1 is given as:
• Move LOC,R1
• Example 2: An instruction that add two numbers contained in
registers R1 and R2 and place the sum in R3 is given as:
• Add R1,R2,R3
Instruction Formats
• A single high level language instruction can be represented in different
machine level instruction format such as:
• Three-Address Instruction
• Two-Address Instruction
• One-Address Instruction
• Zero-Address Instruction
• Let us see how a high level instruction like C = A + B can be represented in
these formats.
• Three-Address Instruction
• Syntax: Opcode source1, source2, destination
• Machine instruction: Add A,B,C
• Meaning: Add the contents of memory location A and B, then place the
result into location C.
• Drawback: More than one words are required to represent the instruction.
Instruction Formats (contd…)
• Two-Address Instruction
• Syntax: Opcode source, destination
• Machine instruction: Add A,B
• Meaning: Add the contents of memory location A and B, place the
result into location B.
• Drawback:
• D1.The content of B is destroyed.
• D2.It also needs more than one words to represent the instruction
• Solution to D1: The content of B can be preserved by using one more
instructions which copies the content of B to C.
• So, we have now two instructions as follows: Move B,C ; Add A,C
Instruction Formats Conventions
• Note: In 2- or 3-address instructions, source operands are specified
first, followed by the destination. This is a convention used in
assembly language expressions for machine instructions in many
computers.
• But, in some other computers it is in reverse order.
• It is also possible that, for a particular computer, its assembly
language may use different order for different instructions.
Instruction Formats (contd…)
• One-Address Instruction
• Syntax: Opcode source/destination
• Machine instructions: Load A; Add B; Store C
• Meaning:
• Load A means copy the contents from location A to Accumulator(AC)
• Add B means add the contents of memory location B to the AC, place
the result back in the AC.
• Store C means copy the contents of AC to location C.
• Note: This can also be implemented without AC, by using any of the
GPRs (say Ri) as follows:
• Load A, Ri ; Add B, Ri ; Store Ri, C
• Drawback: In both the approaches, since one memory address is
directly specified in an instruction, more than one word is required to
represent an instruction like the previous two cases.
Let’s do Better…
• In a processor where arithmetic operations are allowed only on
operands that are in the processor registers, write the machine
instructions for C = A + B
• Move A, Ri
• Move B, Rj
• Add Ri , Rj
• Move Rj ,C
• Which instruction fits to a single memory word?
• Add Ri , Rj
• If a processor has 32 registers, then Ri and Rj needs only 5 bits each
to represent themselves plus some more bits (8 or 16 bits)for opcode
Add. If the word size 32bits, then this instruction fits well into it.
Instruction Formats (contd…)
• Zero-Address Instruction: It contains only opcode, and the operands
are defined implicitly.
• Such instructions are found in machines that stores operands in a
structure called a stack.
• A processor register called as stack pointer (SP) is used to keep track
of the address of the top element.
• It has two basic operations called:
• Push to insert an element into the stack.
• Pop to remove an element from the stack.
Assignment-1 (Submission Deadline-09.11.22)

• Write the machine instructions in assembly language to evaluate

(A+B)  (C+D) in three-Address, two-Address,one-Address, and zero=
address instruction formats.
Instruction Execution and Straight-line
Sequencing
• The instruction execution starts when Begin
execution Address Contents
the first instruction’s address placed here i
inside PC (let it be the instruction at Move A,R0
i+ 4 3-instruction
Add B,R0
address i ). i+ 8
Move R0,C
program
segment
• The control unit uses the content of PC
to fetch the instruction from the
memory and execute. A

• By this time the PC is incremented by 4

Data for
to point to next instruction(instruction B the program
at address i+4).
• In this way, the instructions are executed
C
one at a time, in order of increasing
addresses.
• This is called straight-line sequencing.
Instruction Execution Phases
• Executing an instruction has two basic phases:
• Instruction Fetch
• Instruction Execute
• Instruction Fetch
• Instruction is fetched from memory location whose address is
stored in PC.
• Then the instruction is placed in the IR.
Instruction Execution Phases
• Instruction Execute
• The IR is examined to know which operation is to be performed.
• The specified operation is then performed by the processor. This
involves
• fetching operands from memory/registers,
• performing an arithmetic and logic operation and
• storing the result in the destination location.
• When the execution completes, the PC contains the address
of the next instruction.
• Then a new instruction fetch phase can begin.
Example: Addition of n numbers-Straight-line
Sequencing Move NUM1,R0 i
i+4 Add NUM2,R0
i+8
• Note that, NUM1, NUM2, … NUMn are the Add NUM3,R0
•
symbolic names for the addresses where the n •
•
numbers are stored. i + 4n - 4 Add NUMn,R0
• A separate Add instruction is used to add each i + 4n Move R0,SUM
number to the content of register R0.
•
• After all the numbers added, the result is stored •
•
in memory location SUM. SUM

• Drawback: A long list of Add instructions is NUM1

used. NUM2

•
•
•
NUMn
Branching Move
Clear
N,R1
R0
LOOP
Determine address of
• Instead of a list of Add instructions, we can keep "Next" number and Add
only one Add instruction inside a program loop. Program "Next" number to R0
loop
• The loop is considered to be a straight-line Decrement R1
sequence of instructions executed as many times Branch>0 LOOP
as needed.
Move R0,SUM
• It starts at location LOOP and ends at the
instruction Branch>0.
•
• During each pass, the address of the next •
number is determined, and that is fetched and •
added to R0. SUM
• Then the value of R1 is decremented by 1 N n
(instruction Decrement R1). NUM1
• Therefore, in the beginning of the program, the NUM2
value of n is placed inside R1 with the •
instruction: Move N,R1. •
•
• Also R0 has to be cleared to store the result NUMn
(Clear R0).
Branching (contd…) Move
Clear
N,R1
R0
LOOP
Determine address of
• Execution of the loop is repeated as long as the "Next" number and Add
value of R1>0. Program
loop "Next" number to R0
• The instruction Branch>0 LOOP is a conditional Decrement R1
branch instruction. Branch>0 LOOP
Move R0,SUM
• It causes a branch to location LOOP if the result of
immediately preceding instruction is greater than 0.
It loads a new address in PC called the branch target •
•
instead of the instruction that follows the branch •
instruction. SUM
• In our case the instruction is Decrement R1. N n
NUM1
• At the nth pass the Decrement instruction produces
NUM2
a value 0, hence the branch ends.
•
• Then the PC is incremented in sequential way and •
•
the Move R0,SUM is executed to store the final
NUMn
result from R0 to SUM in the memory.
Condition Codes
• A processor keeps track of the information about the results of various
operations in some flags called condition code flags.
• These are used subsequently by conditional branch instructions.
• A flag can keep only one bit of information as follows:
• N (negative): Set to 1 if the result is negative; otherwise cleared to 0
• Z (zero): Set to 1 if the result is 0; otherwise cleared to 0
• V (overflow): Set to 1 if arithmetic overflow occurs; otherwise cleared to 0
• C (carry): Set to 1 if a carry-out results from the operation; otherwise cleared to 0
• These flags are grouped together in a special processor register called
Condition code register / status register.
• Different instructions affect different flags
• Example: The Branch>0 instruction affects N and Z flags. If the value of N
and Z is 0, then a branch takes place.
Addressing Modes
• High-level language instructions contain many operands in the form
of constants, local/global variables, pointers, arrays etc.
• The different ways in which the location of an operand is specified in
an instruction are referred to as Addressing modes.
• Example: In the addition of n numbers using loop, how to provide
addresses for n numbers in a single Add instruction inside loop?
• One possible solution is:
• let the processor register Ri hold the address of the first number before
starting of the loop, and
• then incremented by 4 on each pass to get the address of next number and
then add.
• Therefore, the objective of the addressing mode is to provide various
methods to specify the address of the operands.
Generic Addressing modes
• Register mode
• Absolute (Direct) mode
• Immediate mode
• Indirect mode
• Index mode
• Base with index
• Base with index and offset
• Relative mode
• Autoincrement mode
• Autodecrement mode
Addressing modes (contd…)
• Register mode: Here the register holds the operand. The
name(address) of the register is given in the instruction.
• Example: Move LOC,R1
• Absolute mode: Here the operand is in the memory location. The
address of the location is given explicitly in the instruction.
• This mode also represent the global variables in a program.
• Example:
1. Move LOC,R1
2. Integer A, B;
Addressing modes(contd…)
• Immediate mode: Here the operand is given explicitly in the
instruction.
• This is only used to specify the value of a source operand.
• The assembly language uses a sharp sign(#) before the value to
indicate the immediate operand.
• Example: Move #200,R0 : It means 200 will be placed inside R0.
• Note: Compilers access the constant values in high-level language by
using the immediate mode.
• Example: Write the assembly language code for A=B+20, assuming A
and B have been declared earlier as variables.
• Solution:
• Move B,R1
• Add #20,R1
• Move R1,A
Addressing modes(contd…)
• Indirect mode: Here, the instruction does not give the operand or its
address explicitly.
• Instead, it provides information from which the memory address of the
operand can be determined. This is called Effective Address(EA).
• Note: The indirect addressing is denoted by placing the name of the
register or the memory address within parenthesis.
• Example 1(Register Indirect): Add (R1),R0
Here the processor uses the value B, which is in register R1, as the effective
address of operand B. Therefore, it needs a read operation from memory to
get the operand at location B.
• Example 2(Memory Indirect): Add (A),R0
Here, the processor first reads the contents of memory location A, then
requests a second read operation using the value of B as the address to
obtain the operand.
Indirection and Pointer
• The register or memory location that contains the address of an
operand is called a pointer.
• Can you identify which one behaves like a pointer in the previous
example?
• Answer: Register R1 and location A.
• That means by changing the contents of R1 or A, the same Add
instruction fetches different operands to add to register R0.
• Note:
• Indirect addressing through registers is used extensively in modern
computers than indirect addressing through memory location.
• When absolute addressing is not available, indirect addressing
through registers make it possible to access global variables by first
loading the operands address in a register.
Use of Indirect Addressing in Addition of n
numbers program
Address Contents
1000 Move N,R1
1004 Move #NUM1,R2 Initialization
1008 Clear R0
LOOP Add (R2),R0
1016 Add #4,R2
1020 Decrement R1
1024 Branch>0 LOOP
1028 Move R0,SUM
Addressing modes(contd…)
• Index mode: It is useful in dealing with the elements of the arrays.
• The effective address (EA) of an operand is generated by adding a
constant value to the contents of a register.
• The register is either a special register or a GPR used to store the
index value, called the index register (Ri).
• Symbolically it is denoted as X(Ri), where X is the constant value
contained in the instruction, also called offset or displacement.
• So, the Effective Address of the operand is given by: EA=X+[Ri]
• Example: Let Ri holds the memory address 1000, and X=4, the
EA=1004. If X=8, then the EA=1008 and so on.
• Note: Another way of using index mode is to represent X as a memory
address and content of Ri is the offset.
Examples
• Write an Add instruction which adds an operand whose address is
available in index register R1 offset by 16 bytes with an operand
stored in R2.
• Add 16(R1),R2
• Write an Add instruction which adds an operand stored in memory
location 2000 whose offset is in index register R1 with an operand
stored in R2.
• Add 2000(R1),R2
Program for finding total marks of a student
• Assume that a student record contains the student id and marks in
three subjects stored in consecutive memory words starting with an
address whose symbolic name is LIST. Write a program to find the
total marks and store it in SUM.
Move #LIST,R0
Clear R1
Add 4(R0),R1
Add 8(R0),R1
Add 12(R0),R1
Move R1,SUM
Addressing modes(contd…)
• Base with Index mode: It is a form of index mode addressing which
uses two registers Ri and Rj
• Rj may be used to contain the offset X.
• Therefore, this mode is denoted as (Ri,Rj).
• So, the effective address is EA=[Ri]+[Rj]
• Note: This form of indexing provides more flexibility in accessing
operands, because both components of EA can be changed.
• Note: This can be used to access elements in two dimensional array.
Addressing modes(contd…)
• Base with index and offset: This form of index mode uses two
registers (Ri,Rj)and a constant X.
• It is denoted as X(Ri,Rj).
• The effective address is given by EA=[Ri]+[Rj]+X
• Note: This can be used to access the elements of a three dimensional
array.
Addressing modes(contd…)
• Relative Mode: It is similar to index mode but, the GPR used
in index mode is replaced with PC.
• It is denoted as X(PC).
• So the effective address is given as EA=[PC]+X.
• So, the EA is X bytes above or below the current content of
PC, where X should be a signed number.
• Note: Since the addressed-location is identified "relative" to
the PC, so it is called Relative mode.
• Note: This mode is used commonly in conditional branch
instructions to specify the target address.
Addressing modes(contd…)
• Note: Branch > 0 LOOP causes program execution to go to
the branch target (BT) location identified by LOOP if branch
condition is satisfied.
• Example:
• In the Addition of n numbers program, when BT address
(LOOP) is generated the PC contains the address 1028.
• So to branch to the address 1012(LOOP), the value needed
in X=-16, since EA=1012=1028+(-16).
Additional Addressing modes
• Although there are five basic modes found in most of the computers,
but there are two additional modes.
• These modes are useful for accessing the data items in successive
memory locations.
• Autoincrement mode:
• The EA of the operand is the contents of a register specified in the
instruction.
• After accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
• This mode is denoted by keeping the specified register in parenthesis,
followed by a plus sign, that is (Ri)+
• Example: Add (R2)+,R0
Autoincrement mode
• Note: The increment amount is 1 for byte size operands, 2 for 16-bit
operands and 4 for 32-bit operands.
• How to implement this concept in the Addition of n numbers program?
Address Contents
1000 Move N,R1
1004 Move #NUM1,R2
1008 Clear R0
LOOP Add (R2)+,R0
1016 Add #4,R2
1020 Decrement R1
1024 Branch>0 LOOP
1028 Move R0,SUM
Autodecrement mode
• Here, the contents of a register specified in the instruction
are first automatically decremented and then used as the EA
of the operand.
• This is denoted by putting the specified register in
parenthesis, preceded by a minus sign like -(Ri).
• Therefore, in this mode, the operands are accessed in
descending address order.
• Note: These two modes are commonly used to implement
the STACKS.
Using Auto-increment/-decrement in STACK
RAM
• Let us take a pushdown stack of word data items 0
in the memory of a computer as shown here. •
•
•
• It is based on the concept of LIFO. SP
1004
• Two basic operations supported are: 1004 20 Top
• PUSH and POP -30 element
• The processor register who keeps track of the top 40
element is called the Stack Pointer (SP). STACK •
•
• Assuming byte addressable memory with 32-bit •
word length, the PUSH can be implemented as: BOTTOM -10 Bottom
• Subtract #4,SP •
element
•
• Move NEWITEM,(SP) •
• Subtract instruction subtracts the source operand NEWITEM
contained in SP and places the result in SP. 2k-1
• Move instruction move the word from location
NEWITEM onto the top of the stack.
Using Auto-increment/-decrement in STACK
• Similarly, the POP can be implemented as:
• Move (SP),ITEM
• Add #4,SP
• Move instruction moves the top value from the stack into location
ITEM.
• Add instruction increments the stack pointer (SP) by 4 bytes, so that it
points to the new top element.
• Write the PUSH and POP operations by using Autodecrement and
Autoincrement modes.
• PUSH can be implemented with a single instruction:
• Move NEWITEM, -(SP)
• POP can also be implemented with a single instruction:
• Move (SP)+,ITEM
 Addressing Mode: Numerical Example

• The two-word instruction at

address 200 and 201 is a “Load Program Counter
to AC” instruction with an
address field equal to 500.
• The first word of the instruction
specifies the operation code and General purpose register
the mode, second specifies the
address part.
• The content of the processor Index register
register R1 is 400, index register
XR is 100.
• Program counter PC has the
value 202. Accumulator register
• Accumulator AC receives the
operand after the instruction is
executed.
 Addressing Effective Content of
Remarks
Mode Address AC

Operand is the contents of the processor register =

Register - 400
400
Program Counter
Absolute or
500 800 EA is the address part of the instruction
Direct

Immediate 201 500 Operand is specified in the instruction

Memory location (500) holds the address of General purpose register

Indirect 800 300 memory location (800), which holds the operand
(300)

EA is calculated by adding the address part of the

Indexed 600 900 Index register
instruction (500) with the indexed register (100)

EA is calculated by adding the address part of the

Relative 702 325 instruction (500) with the contents of PC (202) after
the fetch phase
Accumulator register
Register
400 700 Register specifies the address part of the operand
Indirect

Register specifies the address part of the operand.

Autoincrement 400 700 After the execution of the instruction register is
incremented to 401.

First the register is decremented to 399. After

Autodecrement 399 450 decrement the Register specifies the address part of
the operand.
Subroutines
• A subtask consisting of a set of instructions which is executed many
times is called a Subroutine.
• A Call instruction causes a branch to the subroutine.
• At the end of the subroutine, a Return instruction is executed.
• Program resumes execution at the instruction immediately following
the subroutine Call.
• Subroutine Linkage method: This is a way in which a computer makes
it possible to call and return from subroutines.
• The simplest subroutine linkage method is to save the return address
in a register called the Link Register.
Subroutines(contd…)
• When the subroutine completes its task, the Return instruction
returns to the calling program by branching indirectly through the
Link register.
• The Call Instruction is a special branch instruction that performs the
following operations:
• Store the contents of PC into link register.
• Branch to the target address specified by the instruction.
• The Return Instruction is a special branch instruction that performs
the following operation:
• Branch to the address contained in the link register.
 Example: Subroutine Call and Return
• Call Memory Contents
Address
PC 204 500 0
4
8
Link 204
(A) (B)
Calling
200 Call SUB Program
• Return 204 Next Instruction

PC 540 204
500 First Instruction
Subroutine
SUB
Link 204
540 Return
(C) (D)
Subroutine Nesting
• When one subroutine calls another, it is called subroutine nesting.
• But, the problem is that, how to keep the return address of the second
call?
• Can we keep it in the same Link Register where the return address of the
first subroutine call is stored?
• No. Because it will destroy the return address of the first call.
• Solution: A processor stack has to be maintained since the return
addresses are generated and used in LIFO order.
• A Stack Pointer (SP) is used to point to the top of the stack.
• Call instruction pushes the contents of the PC onto the processor stack and
load the subroutine address into the PC.
• Return instruction pops the return address from the processor stack into
the PC.
Instruction Set Design Issues
• Where are operands stored?
• registers, memory, stack, accumulator
• How many explicit operands are there?
• zero, one, two, or three
• How is the operand location specified?
• register, direct, immediate, indirect (register or memory), relative,
index, auto-increment/decrement. . .
• What type & size of operands are supported?
• byte, int, float, double, string, vector. . .
• What operations are supported?
• Add, Sub, Mul, Div, Move, Branch . . .
ISA Classification
• ISA can be classified as follows, based on where the operands are
stored and whether they are named explicitly or implicitly:
• Single accumulator organization:
• It names one of the general purpose registers as the accumulator and uses it
to store one of the operands.
• That means one of the operands is kept in the accumulator and the other
operand is specified along with the instruction.
• Stack organization:
• Here, the operands are put into the stack and the operations are carried out
on the top of the stack.
• The operands are implicitly specified here.
ISA Classification (contd…)
• General register organization:
• It specifies all the operands explicitly.
• Depending on whether the operands are available in memory or registers, it
can be further classified as: Register-Register and Register-Memory
• Register – register:
• registers are used for storing operands.
• Such architectures are in fact also called load – store architectures, as only
load and store instructions can have memory operands.
• Register – memory:
• one operand is in a register and the other one in memory.
Operand Locations in Four ISA Classes
Code Sequence C = A + B for Four Instruction Sets

Stack Accumulator Register Register-

(register-memory) Register (load-
store)
Push A Load A Load A,R1 Load A,R1
Push B Add B Add B,R1 Load B,R2
Add Store C Store R1,C Add R1, R2, R3
Pop C Store R3,C

memory memory
Reduced Instruction Set Computer (RISC)
• It is a computer architecture in which the instructions are simple.
• That means each instruction performs only one function (e.g. copy a
value from memory to a register, add two values in registers etc.).
• It follows a Load-Store architecture.
• Load–store architecture is an instruction set architecture that divides
instructions into two categories:
• Memory access (load and store between memory and registers) and
• ALU operations (which only occur between registers)
• That means one instruction can’t combine memory access and
computation task (like Add, Sub, Mul etc.)
• Each reduced instruction takes one cycle each.
• Instructions are executed by hardwired control unit
RISC (contd…)
• Fixed length instructions.
• Fewer pre-defined instructions.
• Programming code size is more.
• Few addressing modes, and most instructions have register to register
addressing mode.
• Multiple register set
• Highly pipelined
• Examples: PowerPC, SPARC, RISC-V, ARM, Atmel-AVR and MIPS
• Charles Stark Draper Prize (2022): Steve Furber, John L. Hennessy, David
A. Patterson and Sophie M. Wilson awarded by the United States
National Academy of Engineering
• for their contributions to the invention, development, and implementation of
reduced instruction set computer (RISC) chips.
Practical Applications of RISC
• Mobile systems:
• ARM based Android phones, Apple iphone, ipad
• IBM's PowerPC used in the GameCube, PlayStation 3, Xbox 360 gaming consoles
• MIPS used in the PlayStation, PlayStation 2, Nintendo 64 game consoles
• Atmel-AVR based Xbox game console
• Adruino microcontroller for BMW cars
• Desktop/Laptop computers:
• IBM's PowerPC architecture used in Apple's Macintosh computers;
• Chromebooks use ARM-based platforms;
• Microsoft uses Qualcomm ARM-based processors for its Surface line
• Workstations/Servers/Supercomputers:
• SPARC, by Oracle (previously Sun Microsystems), and Fujitsu.
• PowerPC, and Power ISA were and are used in many of IBM's supercomputers, mid-
range servers and workstations.
• Alpha, used in workstations, servers and supercomputers from Digital Equipment
Corporation, sold to Compaq and then to Hewlett-Packard.
Complex Instruction Set Computer (CISC)
• It is a computer architecture in which single instructions (complex) can
execute several low-level operations.
• It follows a register-memory architecture, means one of the operands
of an operation is in memory, while the other is in a register.
• One instruction can combine memory access and computation
• Such Complex instructions take multiple cycles each.
• Instructions are executed by microprogrammed control unit
• Variable length instructions
• More pre-defined instructions
CISC (contd…)
• Programming code size is less
• Many addressing modes
• Single register set
• No pipelined or less pipelined
• Examples: x86, IBM System/360, z/Architecture, DEC-VAX
 Hardwired Control unit vs Microprogrammed
Control unit
Hardwired Control unit Microprogrammed Control unit
It generates the control signals directly in It generates the control signals through
the hardware. microinstructions.
It is quicker than a microprogrammed It is slower than a hardwired control unit.
control unit.
It is hard to modify. It is easy to modify.
It is more expensive as compared to the It is affordable as compared to the
microprogrammed control unit. hardwired control unit.
It is difficult to manage complex instructions It can easily manage complex instructions.
because the design of the circuit is complex.
It can use limited instructions. It can generate control signals for many
instructions.