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Notes The figure 8.5 depicts the immediate addressing mode.

Figure 8.5: Immediate Addressing

Once the instruction is fetched, the operand is also fetched in the instruction. This reduces the
instruction cycle time. However, the value of the operand is limited because this mode is limited
to the size of the address field.

Index Addressing Mode

Figure 8.6 depicts index addressing mode.

Figure 8.6: Index Addressing

The index addressing mode includes an index register which holds an offset/displacement. The
effective address of the operand is obtained by adding the offset with the contents of the registers
present in the instruction.
The start address of an array in the memory is obtained from the address field in the instruction.
The difference between the start address and the operand address provides an index value for the
operand. The index value is stored in the index register. The operands are stored in consecutive
locations in the memory. Thus, by changing the value of the index or by incrementing the index
value, you can access any operand in the array.
Some CPUs possess auto-indexing feature, which automatically increments the index registers
when an instruction with index addressing is executed.
These addressing modes provide flexibility in writing efficient programs. Addressing modes help
in reducing the instruction length by including a separate field for the address. This helps the
programmers to handle complex tasks such as loop control, program relocations, and indexing of
an array.

8.2 Data Transfer and Manipulation

Computer systems consist of a set of instructions that help the users to easily carry out their
computational tasks. The instruction set differs from one computer system to another. The
operations are represented by binary codes and the binary code assignment in the operation field
of the instruction can be different in different computers. However, the actual operations in the
instruction set are not very different from one computer system to another. The symbolic names
of the instruction (assembly language notation) may also differ from one computer to another.
An instruction usually contains opcode, addressing field, and operand field. There are different
types of opcodes and based on the type of opcode, the instructions can be classified as follows:
1. Data Transfer Instructions
2. Data Manipulation Instructions
3. Program Control Instructions

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Notes
Data transfer instructions transfer data from one location to another without causing any change
in the content present in the binary form. Data manipulation instructions perform arithmetic,
logic, and shift operations. Program control instructions provide decision making abilities and
are able to change the execution sequence. The program control instructions are explained in the
next section.

Data Transfer Instructions

Data transfer instructions move the data between memory and processor registers, processor
registers and I/O devices, and from one processor register to another. There are eight commonly
used data transfer instructions. Each instruction is represented by a mnemonic symbol. Table 8.1
shows the eight data transfer instructions and their respective mnemonic symbols.

Table 8.1: Data Transfer Instructions

Nam e Mnem onic Sym bols

Load LD
Stor e ST
Move MOV
Exchange XCH
Input In
Output OUT
Push PUSH
Pop POP

The instructions can be described as follows:

1. Load: The load instruction is used to transfer data from the memory to a processor register,
which is usually an accumulator.
2. Store: The store instruction transfers data from processor registers to memory.
3. Move: The move instruction transfers data from processor register to memory or memory to
processor register or between processor registers itself.
4. Exchange: The exchange instruction swaps information either between two registers or between
a register and a memory word.
5. Input: The input instruction transfers data between processor register and input terminal.
6. Output: The output instruction transfers data between processor register and output terminal.
7. Push and Pop: The push and pop instructions transfer data between a processor register and
memory stack.
All these instructions are associated with a variety of addressing modes. Some assembly language
instructions use different mnemonic symbols just to differentiate between the different addressing
modes.

Example: The mnemonic symbols for load immediate is LDI

Thus, it is necessary to be familiar with various addressing modes and different types of
instructions to write efficient assembly language programs for a computer.

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Notes
Data Manipulation Instructions
Data manipulation instructions have computational capabilities. They perform arithmetic, logic,
and shift operations on data. There are three basic types of data manipulation instructions:
1. Arithmetic Instructions
2. Logical and Bit Manipulation Instructions
3. Shift Instructions
During execution of the instruction, each instruction goes through the fetch phase, where it reads
the binary code of the instruction from the memory. According to the rules of the instruction
addressing mode, the operands are brought in processor registers. Finally, the instruction in the
processor is executed.

Arithmetic Instructions
Arithmetic operations include addition, subtraction, multiplication and division. Some computers
provide instructions only for addition and subtraction operations, and generate multiplication
and division operations from these two operations. Each instruction is represented by a mnemonic
symbol. Table 8.2 illustrates some of the arithmetic instructions and their respective mnemonic
symbols.

Table 8.2: Arithmetic Instructions

Name Mnem onic

Incr ement INC
Decrement DEC
Add ADD
Subtr act SUB
Multiply MUL
Divide DIV
Add with Carr y ADDC
Subtr act with SUBB
Bor row
Negation NEG

The description of these instructions is as follows:

1. Increment: The increment instruction adds 1 to the value stored in register or memory word.
2. Decrement: The decrement instruction subtracts 1 from the contents stored in register or memory
word.
3. Arithmetic Instructions: The arithmetic instructions are available for different types of data
such as floating point, binary, single precision, or double precision data.
During execution of arithmetic instructions, the processor status flags or conditional codes are set
to designate the outcome of the operation.

Example: For the conditions generated as a carry or borrow, the outcome is either 0 or
negative.

A flip-flop is used to store the carry from an addition operation. The add with carry instruction
performs the addition of two numbers along with the value of carry from the previous computation.
Similarly, the subtract with borrow instruction performs the subtraction of two numbers and a
borrow if any, from the previous computation. The negation instruction represents the 2’s
complement of a number.

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Logical and Bit Manipulation Instructions Notes

Logical instructions carry out binary operations on the bits stored in the registers. In logical
operations, each bit of the operand is treated as a Boolean variable. Logical instructions can change
bit value, clear a group of bits, or can even insert new bit value into operands that are stored in
registers or memory words. Each logical instruction is represented by mnemonic symbols.

Notes Boolean variable is a numerical variable that can hold a single binary bit (0 or 1).

Table 8.3 illustrates some of the logical instructions andtheir respective mnemonic symbols.

Table 8.3: Logical Instructions

Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement COMC
carry
Enable inter rupt EI
Disable interrupt DI

The clear instruction replaces the specific operand by 0’s. The complement instruction inverts all
the bits of the operand and produces 1’s complement. The AND, OR, and XOR instructions perform
logical operations on each bit or group of bits of the operand.
Logical instructions can also manipulate individual bits or group of bits. The bit manipulation
operation can clear a bit to 0, can set a bit to 1, or can complement a bit.
The AND instruction can clear a bit or group of bits of an operand. For Boolean variable a, the
relationship ‘ab0 = 0’ and ‘ab1 = a’ indicates that the binary variable when ANDed with 0 changes
the value to 0. However, the variable when ANDed with 1 does not change the value. Thus, bits
of an operand can be cleared by ANDing the operand with another operand that has to clear all 0
bits in its position. It is also known as mask because it masks 0s in selected bit positions of an
operand.
The OR instruction can set a bit or group of bits of an operand. For Boolean variable a, the
relationship ‘a + 1 =1’ and ‘a + 0 = a’ indicates that the binary variable when ORed with 1, changes
the value to 1. However, the variable when ORed with 0 does not change the value. Thus, OR
instruction is used to set the bits to 1 by ORing the bits of an operand with another operand that
has 1s in its bit positions.
The XOR instruction can complement bits of an operand. For Boolean variable a, the relationship
‘a + 1 = a’ and ‘a + 0 = a’ indicates that the binary variable is complemented when XORed with 1.
However, the variable does not change value when XORed with 0.
The carry bits can be cleared, set, or complemented with appropriate instructions. The bit
manipulation instructions can also enable or disable the interrupt facility, which is controlled by
the flip-flops.
Shift Instructions
Shift instruction helps to shift the bits of an operand to the right or to the left. The direction of
shift is based on specific instructions. The operand is first loaded into the accumulator and then
the shift operation is performed bit by bit.

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Notes The shift-left operation shifts the zero into low-order vacated position.

Example: Operand in Accumulator

1111 0101 1000 1011

After a shift-left operation
1 1110 1011 0001 0110 zero is shifted in

High order bit is shifted out

In shift-right operations, zeros are shifted into high-order vacated position. The bits that are shifted
can also be the original value of the sign bit as in case of arithmetic right shift or can be the bits
that are shifted out of low-order position of the accumulator-extension as in case of Rotate Right
Accumulator and Extension (RRAE). The main purpose of this RRAE is to fetch the bits from the
accumulator-extension position 15 and shift the bits back to the accumulator position 0. This ensures
that no bits are lost during the shift.
The shift operation can be ended either by decrementing the shift count to zero or by shifting the
bit value of 1 into the high-order position (bit 0) of the accumulator.

Example: Consider the below example program to add two numbers:

NAME Addition //name of the program
PAGE 52,80
TITLE 8086 assembly language program to add two numbers //Title of the
program
.model small //implies that the program is a small program
.stack 100 //memory allocation is 100
.data // data for the program
Number1 DB 63H
Number2 DB 2EH
Result DW ?
.code //marks the beginning of the code
START: MOV AX, @data
MOV DS, AX
MOV AL, Number1
ADD AL, Number2
MOV AH, 00H
ADC AH, 00H
MOV Result, AX
END START

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In the above program, Notes

1. .model specifies the mode for assembling the program.
2. DB allocates and initializes the bytes of storage.
3. Number1 DB 63H indicates the first number storage and Number2 DB
2EH indicates the second number storage.
4. DW allocates and initializes the words of storage.
5. Result DW indicates that double byte is reserved for the result.
6. The instructions MOV AX, @data and MOV DS, AX initialize the data
segment.
7. MOV AL, Number1 transfers the first number to AL.
8. ADD AL, Number2 adds the second number to AL.
9. MOV AH, 00H makes Most Significant Bit of result zero.
10. ADC AH, 00H puts carry in AH.
11. MOV Result, AX copies result to the memory.

8.3 Program Control

Instructions of the computer are always stored in consecutive memory locations. These instructions
are fetched from successive memory locations for processing and executing. When an instruction
is fetched from the memory, the program counter is incremented by 1 so that it points to the
address of the next consecutive instruction in the memory. Once a data transfer and data
manipulation instruction is executed, the program control along with the program counter, which
holds the address of the next instruction to be fetched, is returned to the fetch cycle.
Data transfer and manipulation instructions specify the conditions for data processing operations,
whereas the program control instructions specify the conditions that can alter the content of the
program counter. The change in the content of program counter can cause an interrupt/break in
the instruction execution. However, the program control instructions control the flow of program
execution and are capable of branching to different program segments.
Some of the program control instructions are listed in table 8.4.

Table 8.4: Progr am Contr ol I nstructions

Name Mnemonic
Branch BR
Jum p JMP
Skip SKP
Call CALL
Return RET
Compare (by CMP
subtraction)
Test (by ANDing) TST

The branch is a one-address instruction. It is represented as BR ADR, where ADR is a mnemonic

for an address. The branch instruction transfers the value of ADR into the program counter. The
branch and jump instructions are interchangeably used to mean the same. However, sometimes
they denote different addressing modes.

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Notes Branch and jump instructions can be conditional or unconditional. The unconditional branch
instruction creates a branch to the specified address without any conditions.

Example: JMP Displaydiagram

The JMP instruction transfers the flow of execution, without considering the
actual condition of the flags, to the indicated operator. The above instruction
makes the control jump to the part of the code where Displaydiagram is
specified.
The conditional branch instructions such as ‘branch if positive’, or ‘branch if zero’ specify the
condition to transfer the flow of execution. When the condition is met, the branch address is loaded
in the program counter.
Figure 8.7 depicts the conditional branch instructions.

Figure 8.7: Conditional Branch

The compare instruction performs an arithmetic subtraction. Here, the result of the operation is
not saved; instead, the status bit conditions are set. The test instruction performs the logical AND
operation on two operands and updates the status bits.

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Status Bit Conditions Notes

The status register comprises the status bits. The bits of the status register are modified according
to the operations performed in the ALU. Figure 8.8 depicts a block diagram of an 8-bit ALU with
a 4-bit status register.

Figure 8.8: Status Register Bits

In figure 8.8, if the end carry C 8 is 1, then carry (C) is set to 1. If C 8 is 0, then C is cleared to 0.
If the highest order bit F7 is 1, then Sign (S) is set to 1. If F7 is 0, then S is set to 0.
If the output of ALU is 0, then zero (Z) is set to 1, otherwise Z is set to 0.
If XOR of the last two carries is equal to 1, then overflow (V) is set to 1, otherwise V is cleared to
0.
The result of the 8-bit ALU operation is either 127 or -127.
Z is a status bit used to indicate the result obtained after comparing A and B. Here, XOR operation
is used to compare two numbers (Z = 0 if A = B).

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Notes Conditional Branch Instruction

The conditional branch instruction checks the conditions for branching using the status bits. Some
of the commonly used conditional branch instructions are shown in table 8.5.

Table 8.5: Conditiona l Instructions

Mnemonic Condition Tested

Condition
BZ Br anch if zer o Z=1
BNZ Br anch if not zero Z=0
BC Br anch if carry C=1
BNC Br anch if no carr y C=0
BP Br anch if plus S=0
BM Br anch if minus S=1
BV Br anch if overflow V=1
BNV Br anch if no overflow V=0
Unsigne d com par e conditions (A – B)
BHI Br anch if higher A >B
BHE Br anch if higher or equal A B
BLO Br anch if lower A <B
BLOE Br anch if lower or equal A B
BE Br anch if equal A =B
BEN Br anch if not equal A B
Signed compare cond itions (A – B)
BGT Br anch if greater than A >B
BGE Br anch if greater or equal
A B
BLT Br anch if less than A <B
BLE Br anch if less or equal
A B
BE Br anch if equal A =B
BEN Br anch if not equal A B

Thus, when the status condition is true, the program control is transferred to the address specified
in the instruction, otherwise the control continues with the instructions that are in the subsequent
locations. The conditional instructions are also associated with the program control instructions
such as jump, call, or return.
The zero status bit checks if the result of the ALU is zero or not. The carry bit checks if the most
significant bit position of the ALU has a carry out. It is also used with rotate instruction to check
whether or not the bit is shifted from the end position of a register into a carry position. The sign
bit indicates the state of the most significant bit of the output from the ALU (S = 0 denotes positive
sign and S = 1 denotes negative sign). The branch if plus and branch if minus are used to check
whether the value of the most significant bit represents a sign or not. The overflow and underflow
instructions are used in conjunction with arithmetic operations performed on signed numbers.
The higher and lower words are used to denote the relations between unsigned numbers, whereas
the greater and lesser words are used to denote the relations between signed numbers.

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Notes
Example: Consider two numbers M = 11110000 and N = 00010100. When we perform
M - N operation, the result obtained is
M: 11110000
N: 00010100
M-N: 11011100
The compare instruction updates the status bits:
C =1: Carry out of the last stage
S = 1: Left most bit is 1
Z = 0: Last two carries are equal to 1
V = 0: Result is not equal to 0
Consider the numeric value, where M = 60 and B =10 (unsigned numbers).
Here, M > N and M N. Therefore, the instructions that will cause branch
are BHI, BHE and BNE.
If M = -8 and N = 10, then we have M < N and M N. Therefore, the
instructions that will cause branch are BLT, BLE, and BNE

8.4 RISC and CISC

The design of the instruction set for the processor is considered as an important aspect of computer
architecture. The machine language program is developed based on the instruction set chosen for
that particular computer.
Earlier, the hardware components of the computer were expensive and to minimize this expense,
the programmers started to build simple and small instructions. With the advent of integrated
circuits, the digital hardware became cheaper and the computer instructions started to increase in
number and complexity. Many computers have more than 100 instruction sets. Such computers
with large number of instructions are classified as a Complex Instruction Set Computers (CISC).
In 1980s, computer architects started to design computers with fewer instructions in order to execute
programs at a much faster rate within the CPU. Such computers with less number of instructions
are classified as a Reduced Instruction Set Computer (RISC).

Complex Instruction Set Computer (CISC)

A Complex Instruction Set Computer (CISC) comprises a complex instruction set. It incorporates
variable length instruction format. Instructions that require register operands may take only two
bytes. However, the instructions that require two memory addresses may take five bytes to include
the complete instruction code. Thus, CISC has variable length encoding of instructions and the
execution of instructions may take varying number of clock cycles. The CISC processor provides
direct manipulation of operands that are in memory.

Example: An ADD instruction will use index addressing to specify one operand in memory
and direct addressing to specify second operand in memory. This instruction would use another
memory location to store the result. Thus, this instruction would use three memory references for
execution.
Many CISC architectures read the inputs and write their outputs in the memory system instead of
a register file. As CISC architecture takes large number of addressing modes, more hardware
logic is required to implement them. This reduces the computation speed.
Basically, the CISC architecture attempts to provide a single machine instruction for the statements
that are written in a high-level language.

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Notes
Example: The IBM 370 computer uses the CISC architecture.

Reduced Instruction Set Computer (RISC)

In Reduced Instruction Set Computer (RISC) architecture, the instruction set of the computer is
simplified to reduce the execution time. RISC has a small set of instructions, which generally
include register-to-register operations. Thus, data is stored in processor registers for computations
and results of the computations are transferred to the memory using store instructions. All
operations are performed within the registers of the CPU. In RISC, all instructions have simple
register addressing and hence use less number of addressing modes.
RISC uses relatively a simple instruction format and is easy to decode. Here, the instruction length
can be fixed and aligned on word boundaries. The RISC processors have the ability to execute one
instruction per clock cycle. This is done using pipelining, which involves overlapping the fetch,
decode, and execute phases of two or three instructions.
As RISC takes relatively a large number of registers in the processor unit, it takes less time to
execute its program when compared to CISC.

Example: The Scalable Processor Architecture (SPARC) is an example of RISC architecture.

8.4.1 RISC Instruction Set

RISC instruction set includes simpler instructions with hard-wired control, large number of
registers, simpler processor pipeline and increased clock-rate. The RISC processor’s instruction
set is restricted to load and store instructions when there is an interaction between memory and
CPU. All other instructions are executed within registers without any reference to memory.

Example: Consider an example program for a RISC-type CPU, which include load and store
instructions that have one memory and one register address, and arithmetic instructions that are
specified by processor registers. The below program evaluates X = (P + Q)*(R + S)
LOAD R1 P R1 M[P]
LOAD R2 Q R2 M[Q]
LOAD R3 R R3 M[R]
LOAD R4 S R4 M[S]
ADD R1, R1, R2 R1 R1 + R2
ADD R3, R3, R4 R3 R3 + R4
MUL R1, R1, R3 R1 R1 + R3
STORE X, R1 M[X] R1
The LOAD instructions transfer the operand P, Q, R and S from memory to CPU
registers R1, R2, R3, and R4 respectively. The ADD and MUL instructions execute
the addition and multiplication operations with the data in the registers without
referring to the memory. The STORE instruction stores the result of the
computation in the memory (M[X]).

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8.4.2 RISC Versus CISC Notes

There are some significant differences between RISC and CISC processors. The comparison between
the common characteristics of RISC and CISC processor is shown in table 8.6:

Table 8. 6: Comparison Between RI SC and CISC

RISC CISC
Few instructions Many instructions
Few addr essing modes. Most Many addressing modes
instructions have register to
register addressing modes
Includes simple instructions and Includes complex instr uctions and
takes one cycle takes multiple cycles
Some of the instructions refer to Most of the instr uctions r efer to
memory memory
Hardwar e executes the Microprogram executes the
instructions instr uctions
Fixed format instructions Var iable forma t instructions
Easier to decode as instructions Difficult to decode as instructions
have fixed for mat have variable format
Multiple register sets are used Single r egister set is used
RISC is highly pipelined CISC is not pipelined or less
pipelined
Load and store functions are Load and stor e functions are found
separate instr uctions in a single instr uction

Today, RISC and CISC architectures are becoming more alike. Many RISC chips now support
instructions of CISC chips also. Similarly, CISC chips are using many techniques associated with
RISC chips.

8.5 Summary
• Addressing modes provide different methods for specifying operand address in the instruction.
• Some of the commonly used addressing modes are direct addressing mode, indirect addressing
mode, register addressing mode, immediate addressing mode, and index addressing mode.
• Data transfer instructions help to move the data from one location to another. Data manipulation
instructions perform arithmetic, logic, and shift operations on data.
• Program control instructions specify the conditions for data processing operations.
• The Complex Instruction Set Computer (CISC) consists of many complex instruction sets.
• The Reduced Instruction Set Computer (RISC) consists of less instruction sets and executes the
instructions at a greater speed.

8.6 Keywords
Accumulator: A processor register that stores intermediate arithmetic and logic results.
Flip-flops: An electronic circuit that is interconnected to form logic gates. It changes its state when
it receives the input pulse (trigger). Hence, it is also known as bistable gate.
Microprogram: A computer program that has basic elemental commands which control the
operation of each components of a microprocessor.
Pipelining: In pipelining, while the processor is performing arithmetic operations, the computer
architecture allows the next instructions to be fetched, holding them in a buffer close to the
processor until each instruction operation can be performed.

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