Centre for Distance & Online Education

INTERNAL ASSIGNMENT

NAME ANKUR KUMAR

ROLL 2314511354
PROGRAM BACHELOR OF COMPUTER APPLICATION
SEMESTER II
COURSE NAME DIGITAL LOGIC
COURSE CODE DCA1205

SET-I

Q1. Explain the various Boolean laws with logic diagrams.

The various laws of Boolean algebra are:

1. Commutative Law:
Commutative Law states that the order of variables does not matter in any of the Boolean
operations. For two variables, the commutative law of addition is a+b = b+a and the
commutative law of multiplication is a.b = b.a
These can be represented through logic diagrams as follows:

A B
A+B B+A
B A

A B
A.B B.A
B A
2. Associative Law
This law states that the operation can be performed in any order when the variables priority is
same. As '*' and '/' have same priority. In the below diagram, the associative law is applied to
the 2-input OR gate. For three variables, the associative law of addition is written as:
A + (B + C) = (A + B) + C
A A A(BC)
A(BC)
B
B
C C

Page 1 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

The associative law of multiplication is written as:

A(BC) = (AB)C

3. Distributive Laws:
According to this law, if we perform the OR operation of two or more variables and then
perform the AND operation of the result with a single variable, then the result will be similar
to performing the AND operation of that single variable with each two or more variable and
then perform the OR operation of that product. This law explains the process of factoring.
For three variables, the distributive law is written as:
A(B + C) = AB + AC
A
B
B
B+C Y
C
A
A Y
C

Y= A (B + C) Y= AB + AC

4. Involution Law:

(A’)’= A

A=1 A=0

A=0 A=0 A=1 A=0

5. Complementary Law:

A+A’ = 1
A=1
A=0 Y=1
Y=1
A=1 A=0

A.A’ = 0

A=0 A=1
Y=1
Y=0 A=1
A=0
6. Idempotent Law:

A+A=A
A=1
A=0 Y=1
Y=0 A=1
A=0
Page 2 of 13 Mail id: [email protected]
Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

A.A = A

A=0 A=1
Y=0 Y=0
A=0 A=1

7. Identity Law:

A+0 = A

A=1 A=0 Y=0

Y=1 0
0

A.1 = A

A=0 A=1
Y=0 Y=1
1 1

8. DeMorgans Law:

(AB)’ = A’ + B’ A
A
A
Y = AB Y=A+B
B
B
B

(A + B)’ = A’B’
A
A
A Y=AB
Y=A+B
B B
B

Q2. Define the term logic gates. Explain the various basic gates with their symbols and
truth table.
A logic gate is an electronic circuit which has one or more inputs but only one output. Logic
gate produces logical operation on binary numbers. The various types of gates are:

1. OR Gate: OR gate has two or more inputs and only one output. The operation of this gate is
such that it produces a high output (i.e. logic 1) when one or more of inputs are high and it

Page 3 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
produces a low output (i.e. logic 0) when all the inputs are low. The logic symbol, truth table
and Boolean expression for 2-input OR gate is shown in figure below

A
A+B Y=A+B
B

(a) (b)

OR gate (a) Logic symbol (b) Boolean expression

Note that A and B are the inputs and Y is the output. The Boolean expression Y = A + B is
read as Y equals A OR B.

A B Y
0 0 0
0 1 1
1 0 1
1 1 1

(c) Truth table

2. AND Gate: AND gate has two or more inputs and only one output. This gate produces a
high output (i.e. logic 1) when all of inputs are high and it produces a low output (i.e. logic 0)
when one or more of its inputs are low.

A
A.B Y= A.B
B
(a) (b)

AND gate (a) Logic symbol (b) Boolean expression

A B Y
1 1 1
0 1 0
1 0 0
0 0 0

Truth table

Here A and B are the inputs and Y is the output. The Boolean expression Y = A.B is read as Y
equals A AND B.

Page 4 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
3. NOT gate: A NOT gate has only one input and only one output. This gate produces the
output which is the inversion (i.e. complement) of the input. Suppose if the input is 1(HIGH),
then its output is 0 i.e. logic 0 (LOW). NOT gate is also known as an inverter. If the input
variable is A, the inverted output is known as NOT A. This can also be shown as A', or A with
a bar over the top i.e. A .

A Y Y=A

(a) Logic Symbol (b) Boolean Expression

A Y
1 0
0 1

Truth Table
Universal Gates
NAND Gate:
The NAND gate is a digital logic gate that behaves in a manner that corresponds to the truth
table to the left. When both the inputs to NAND gate are high, then output of the gate will be
LOW. The output of gate will be HIGH when one or both the inputs of NAND gate are LOW.
As any type of gate or Boolean function can be implemented using NAND gates, they are also
known as Universal gates.
Distinctive NAND Symbol Rectangular NAND Symbol

&
A
Out
B

X Y X|Y
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate:

The NOR gate is a digital logic gate and it behaves such that when both the inputs of NOR gate
are LOW, the output of the gate will be HIGH. A LOW output results when one or both inputs
of the NOR gate are HIGH. Negation of OR gate output results in NOR. NOR is a functionally
complete operation – As any type of gate or Boolean function can be implemented using NOR
gates, they are also known as Universal gates. As the OR operator can change LOW to HIGH
but not vice versa, it is said to be monotonic.

A >1
Page 5 of 13 out Mail id: [email protected]
B Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

X Y X?Y
0 0 1
American NOR Symbol 0 1 0 IEC NOR Symbol
1 0 0
X Y X?Y 1 1 0
0 0 1
0 1 0
1 0 0
1 1 0

XOR Gate:
The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive
disjunction – it behaves according to the truth table to the right. If either one of the input is
HIGH, then the output will be HIGH. The output of the gate results a LOW value when either
the inputs of the gate are LOW or both are HIGH.

A A B A XOR B
A XOR B 0 0 0
B
0 1 1
1 0 1
1 1 0
Logical Symbol of XOR Gate

X-NOR Gate

The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR (XOR)
gate. The two-input version implements logical equality, behaving according to the truth table
to the right. If the inputs to XOR gate are same, then the output will be HIGH. A LOW output
will result if both the inputs to the XOR gate are not same.

A B A XNOR B
0 0 1
0 1 0
1 0 0
1 1 1

A
out
B

X-NOR Symbol

Page 6 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
Q3. Explain the method of Karnaugh map simplification with don’t care condition. Give
example..

A Karnaugh map (K-map) is a visual representation of a Boolean functions. The simple

functions in Boolean function are known as product function; product functions can be product
of few variables or all variables. Sometimes, in a Boolean expression for certain input
combinations, the value of the output is not specified either due to invalid input combinations
or due to the precise value of output is of no importance. These input combinations for which
the values of the Boolean function are not specified are called don’t care combinations. Don’t
care combinations are also referred to as optional combinations. In K-map, don’t care
combinations are represented by "X" or "d" or "ϕ". When we deal with SOP (Sum of Products)
K-map, each don’t care term is treated as a 1, if it helps in reduction of the expression, otherwise
it is considered as a 0 and left alone. On the other hand, when we are using POS (Product of
Sums) K-map, each don’t care term is considered as a 0, if it is helpful in reduction of the
expression, otherwise it is treated as a 1 and left alone. The "Don't care" condition says that we
can use the blank cells of a K-map to make a group of the variables. To make a group of cells,
we can use the "don't care" cells as either 0 or 1, and if required, we can also ignore that cell.
We mainly use the "don't care" cell to make a large group of cells. The cross(×) symbol is used
to represent the "don't care" cell in K-map. This cross symbol represents an invalid
combination. The "don't care" in excess-3 code are 0000, 0001, 0010, 1101, 1110, and 1111
because they are invalid combinations. Apart from this, the 4-bit BCD to Excess-3 code, the
"don't care" are 1010, 1011, 1100, 1101, 1110, and 1111.
We can change the standard SOP function into a POS expression by making the "don't care"
terms the same as they are. The missing minterms of the POS form are written as maxterms of
the POS form. In the same way, we can change the standard POS function into an SOP
expression by making the "don't care" terms the same as they are. The missing maxterms of
the SOP form are written as minterm of the SOP form.
The “Don’t Care” conditions allow us to replace the empty cell of a K-Map to form a
grouping of the variables which is larger than that of forming groups without don’t care.
While forming groups of cells, we can consider a “Don’t Care” cell as 1 or 0 or we can also
ignore that cell. Therefore, the “Don’t Care” condition can help us to form a larger group of
cells.
Example: Consider a 3-variable Boolean function F(A,B,C)F(A, B, C)F(A,B,C) with the
following minterms and don’t care conditions:
Minterms (1s): F(0,0,1)F(0,0,1)F(0,0,1), F(0,1,0)F(0,1,0)F(0,1,0), F(1,1,0)F(1,1,0)F(1,1,0)
Don’t cares (Xs): F(1,0,1)F(1,0,1)F(1,0,1), F(1,1,1)F(1,1,1)F(1,1,1):
Construct the K-map:
AB \ C 0 1
00 01
01 10
11 1X
10 0X
Fill in the K-map with minterms and don’t care conditions.
Group the 1s and don’t cares:
Group 1: Includes F(0,1,0)F(0,1,0)F(0,1,0) and F(1,1,0)F(1,1,0)F(1,1,0)

Page 7 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
Group 2: Includes F(0,0,1)F(0,0,1)F(0,0,1) and F(1,0,1)F(1,0,1)F(1,0,1) (taking advantage of
the don’t care condition)
AB \ C 0 1
00 01
01 10
11 1X
10 0X
Write the simplified expression:
For Group 1 (covering F(0,1,0)F(0,1,0)F(0,1,0) and F(1,1,0)F(1,1,0)F(1,1,0)):
B=1B = 1B=1 (since B is 1 in both minterms in the group)
C=0C = 0C=0 (since C is 0 in both minterms in the group)
Therefore, the group simplifies to B⋅C‾B \cdot \overline{C}B⋅C
For Group 2 (covering F(0,0,1)F(0,0,1)F(0,0,1) and F(1,0,1)F(1,0,1)F(1,0,1)):
C=1C = 1C=1 (since C is 1 in both minterms in the group)
Therefore, the group simplifies to CCC
Thus, the simplified Boolean expression is: F(A,B,C)=B⋅C‾+CF(A, B, C) = B \cdot
\overline{C} + CF(A,B,C)=B⋅C+C

SET-II

Q4. Explain the working of JK flip flop?

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting
the S = R = 1 condition as a "flip" or toggle command. The flip flop will be set when J is 1 and
K is 0; and flip flop will be reset when J is 0 and K is 1; the output of the flip flop will toggle
when both J and K are 1. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will
hold the current state. The D flip flop can be obtained from JK flip flop by setting complement
of J to K. As JK flip flop can be configured to any of other 3 flip flops (SR, D, T), it is
considered as Universal flip flop. The figure below shows the logic symbol of JK flip-flop.

The symbol of JK flip flop

Page 8 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
In the JK flip flop circuit symbol, the clock input is shown as > and data inputs are J, K. Q and
Q are the data outputs. The characteristic equation of the JK flip-flop is:
Qnext = JQ + KQ
and the corresponding truth table is

Truth table for the operation of JK flip-flop

A JK flip-flop is a type of digital storage element used in sequential logic circuits. It is a

refinement of the SR flip-flop (Set-Reset flip-flop) with additional functionality to eliminate
the indeterminate state present in the SR flip-flop. The JK flip-flop has two inputs, J and K,
along with a clock input and often a reset (or clear) and set (or preset) input.

Working Principle of a JK Flip-Flop

The JK flip-flop operates based on the state of its inputs (J and K) and the clock signal.
Inputs:
J (Set): This input sets the flip-flop.
K (Reset): This input resets the flip-flop.
Clock: The flip-flop is edge-triggered, meaning it changes state on the rising or falling edge of
the clock signal.
Preset and Clear: These asynchronous inputs force the output to a set or reset state, irrespective
of the clock.
Outputs:
Q: The main output of the flip-flop.
Q': The complement of Q (not Q).
JK Flip-Flop Truth Table
Explanation of Operation:
J = 0, K = 0 (Hold State):
When both J and K are 0, the flip-flop holds its current state, meaning Q remains unchanged.
J = 0, K = 1 (Reset):
When J is 0 and K is 1, the flip-flop resets, setting Q to 0.
J = 1, K = 0 (Set):
When J is 1 and K is 0, the flip-flop sets, setting Q to 1.
J = 1, K = 1 (Toggle):
When both J and K are 1, the flip-flop toggles its state. If Q was 0, it becomes 1, and if Q was
1, it becomes 0.

Page 9 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

Timing Diagram of JK Flip Flop

Q5. Explain the shift register in detail.

Shift Register is a set of binary storage elements, typically flip-flops combined and linked
together to facilitate the movement of the data bits stored, from one to another and in and out
of it, whenever desired by activating control signals. Inputs to the shift registers can be serial
or parallel. Similarly outputs of the shift registers can be serial or parallel. Thus we can have
four types of shift registers based on the serial or parallel nature of inputs and outputs.
They are listed below.
 Serial Input Serial Output (SISO)
 Serial Input Parallel Output (SIPO)
 Parallel Input Serial Output (PISO)
 Parallel Input Parallel Output (PIPO)
There are bi-directional shift registers that allow shifting of data bits in both directions, i.e.
from left to right and vice versa. If we connect inputs and outputs of a serial-in serial-out shift
register, we get so called circular shift register.
Serial-In Serial-Out (SISO): As the name suggests, data bits are stored in serially and in the
same way these get out of the shift register serially. The string of bits that we want to shift in
are given to the input pin named ‘Data In’. Each bit presented at ‘Data In’ is shifted to its right
one flip-flop at a time, every time ‘Data Shift’ signal is enabled. First time, the bit on ‘Data In’
line is moved into the first ‘flip-flop’s output. The data bit on the rightmost flip-flop gets shifted
out through the output line of the shift register ‘Data Out’. The bit that goes out through ‘Data
Out’ is lost.

Data In Data Out

Serial-In Serial-Out

Serial-In Parallel-Out (SIPO) This is almost similar to SISO shift register except that the data
are readout in parallel at the same time. this means, we can input the data bits into this shift
register serially via ‘Data In’ input line and data can be read out in parallel from data out lines.

Page 10 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

Serial-In Parallel-Out

Parallel-In Serial-Out (PISO): In Parallel-In, Serial-Out (PISO) shift register, the data input is
given in parallel to the input line of each of the flip-flops and outputs are readout serially from
single output line (Data Out).

Parallel-In Serial-Out

Parallel-In Parallel-Out (PIPO): The PIPO register is mainly used to shift a given set of bits
and present it to the next stage as illustrated below. Input for shifting can be loaded into the
register in parallel and the shifted output can be read out of the register in parallel as well.
Hence the name PIPO shift register.

Page 11 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education

Parallel-In Parallel-Out

Q6. Discuss about the Master slave flip flop

A master-slave flip flop is a digital circuit built by cascading two regular flip flops (like JK flip
flops) to overcome a limitation in standard designs. Here's a breakdown of how it works:
Basic Idea:
Imagine two flip flops, one called the master and the other the slave. The master takes the data
input and reacts to the clock signal first. The slave, however, is isolated from the input until the
clock signal instructs it to copy the data from the master.

Master-slave (pulse-triggered) D flip-flop: By connecting two gated D latches in series, a

master-slave D flip flop can be constructed. In this master-slave D flip flop one of the two gated
is connected to active low enable. As the second flip flop responds for the changes from first
flip flop (master) this circuit is called master slave. The circuit is said to be pulse triggered if
the data is accepted at the positive edge of the clock and that value is reflected at the output at
the negative edge of the clock.

Master-slave (pulse-triggered) D flip-flop

Page 12 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)
 Centre for Distance & Online Education
Usually a master slave flip flop responds during the negative edge of the enable input. When
the clock input low for a positive edge triggered master slave D flip flop and enable to the
master is high. During the transition of clock from low to high, the input value will be latched.
When the clock is changed from 0 to 1, the enable to the master will go low and its locks the
value which is at master’s input. At the same time, the enable to the slave will be changed from
low to high and the signal which is captured by the master is latched by the slave. When the
clock signal is changed from high to low, the output of the slave is locked and holds the value
which is seen at the last positive edge while the master accepts the new value.
J-K Master Slave Flip Flop The logic symbol for the master-slave flip-flop only indicates the
initial inputs to the master and the outputs from the slave. Master-slave flip flop is designed
using two separate flip flops. One acts as the master and the other as a slave.
When clock signal i.e. Clk=1, the master J-K flip flop gets disabled. The Clk input of the master
input will be the opposite of the slave input. So the master flip flop output will be recognized
by the slave flip flop only when the Clk value becomes 0. So when the clock pulse makes a
transition from 1 to 0, the locked outputs of the master flip flop are fed through to the inputs of
the slave flip-flop making this flip flop edge or pulse-triggered.

Page 13 of 13 Mail id: [email protected]

Phone: +91 79966 00444 (Toll
Free)