Chapter 3: NMOS and PMOS transistors

N-MOS Transistor

The following figure shows a three-dimensional view, cross section, and circuit symbol of an n-channel MOSFET,
usually called an NMOStransistor, or NMOSFET. The two heavily doped n-type regions (n regions), called the
source S and drain D, are formed in the p-type substrate and nearly aligned with the edge of the gate. The source
and drain provide a supply of carriers so that the inversion layer can rapidly form in response to the gate voltage.
The substrate of the NMOS transistor represents a fourth device terminal and is referred to synonymously as the
substrate terminal, or the body terminal B.

Drain current iD , source current IS, gate current IG, and body current iB are all defined, with the positive direction of
each current indicated for an NMOS transistor. The important terminal voltages are the gate-source voltage
vGS = vG - vS, the drain-source voltage vDS = vD - vS and the source-bulk voltage vSB = vS - vB. These voltages are all
positive during normal operation of the NMOSFET.
Note that the source and drain regions form pn junctions with the substrate. These two junctions are kept reverse-
biased at all times to provide isolation between the junctions and the substrate as well as between adjacent MOS
transistors. Thus, the bulk voltage must be less than or equal to the voltages applied to the source and drain
terminals to ensure that these pn junctions are properly reverse-biased.

The semiconductor region between the source and drain regions directly below the gate is called the channel
region of the FET, and two dimensions of critical import are: L represents the channel length, which is measured
in the direction of current in the channel. W is the channel width, which is measured perpendicular to the direction
of current. Choosing the values for W and L is an important aspect of the digital and analog IC designer’s task.

For a dc gate-source voltage, VGS, well below threshold voltage VTN back-to-back pn junctions exist between the
source and drain, and only a small leakage current can flow between these two terminals. For VGS near but still below
threshold, a depletion region forms beneath the gate and merges with the depletion regions of the source and drain.
The depletion region is devoid of free carriers, so a current still does not appear between the source and drain.

Finally, when the gate-channel voltage exceeds the threshold voltage VTN, electrons flow in from the source and
drain to form an inversion layer that connects the n+ source region to the n+ drain. A resistive connection, the
channel, now exists between the source and drain terminals.

If a positive voltage is applied between the drain and source terminals, electrons in the channel inversion layer will
drift in the electric field, creating a current in the terminals. Positive current in the NMOS transistor enters the drain
terminal, travels down the channel, and exits the source terminal. The gate terminal is insulated from the channel;
thus, there is no dc gate current, and IG = 0. The drain-bulk and source-bulk (and induced channel-to-bulk) pn
junctions must be reverse-biased at all times to ensure that only a small reverse-bias leakage current exists in these
diodes. This current is usually negligible with respect to the channel current ID and is neglected. Thus we assume
that IB = 0.
The drain-source current for the NMOS transistor in its linear region or triode region of operation, in which a
resistive channel directly connects the source and drain is given by:

(1)

The i -v characteristics in the triode region generated from equation (1) are drawn in the following figure for the
case of VTN = 1 V and Kn = 250 A/V2.

The curves represent a portion of the common-source output characteristics for the NMOS device. The output
characteristics for the MOSFET are graphs of drain current iD as a function of drain-source voltage vDS. A family of
curves is generated, with each curve corresponding to a different value of gate-source voltage vGS. The output
characteristics appear to be a family of nearly straight lines, hence the alternate name linear region (of operation).
However, some curvature can be noted in the characteristics, particularly for VGS= 2V.

The current iD through the MOSFET is directly proportional to the voltage vDS across the MOSFET. The FET
behaves much like a resistor connected between the drain and source terminals, but the resistor value can be
controlled by the gate-source voltage. It has been said that this voltage-controlled resistance behavior originally
gave rise to the name transistor, a contraction of “transfer-resistor.”
The resistance of the FET in the triode region near the origin, called the on-resistance Ron, is defined as:

(2)

(3)

SATURATION OF THE i -v CHARACTERISTICS

Equation (1) is valid as long as the resistive channel region directly connects the source to the drain. However, as
the drain voltage increases above the triode region limit, the current does not continue to increase, but instead
saturates at an almost constant value. This region of operation of the MOSFET is often referred to as either the
saturation region or the pinch-off region of operation.

Exercise: Explain why the drain current is constant (and not zero) at the pinch-off region (refer to your text).

The expression for the NMOS current in the saturation region of operation is given by:

(4)
The value of vDS for which the transistor saturates (saturation voltage, or pinch-off voltage) is given by:

The overall output characteristics for an NMOS transistor with VTN = 1V and is shown below.
Transconductance for the saturation region is given by:

(5)
The larger the device transconductance, the more gain we can expect from an amplifier that utilizes the transistor.

For all regions, the mathematical model of NMOS tranistor are summarized as follows:

For PMOS,