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Impact College of Engineering and Applied Sciences

Department of ECE
Advanced VLSI
Assignment -2 Max marks: 10
Date issued : 28/11/24 Date of submission: 17/12/24

Answer any 5 questions from each module.


Module 3
1.) Write a note on Randomization. Which input designs can be randomized?
2.) Explain functional coverage
3.) Explain the different layers in testbench
4.) What is directed testing?
5.) Explain the built in data-types in system verilog
6.) Create an array, initialize the array with 5 elements, change first three elements of the same array, change last two
values as -1
7.) Explain i) for and for each ii) copy and compare iii) bit and array subscripts iv) dynamic arrays v) packed arrays
8.) Write a note on queues.
9.) i) Declare an array perform sorting, reverse sorting and shuffling ii) declare two arrays and find the minimum,
maximum and unique values iii) Array locator methods: find
10.) How to choose a right storage type?
11.) Write a note on choosing the best data structure
12.) Explain streaming operators
13.) Explain enumerated types
14.) Explain constants and strings in enumerated types
Module 4
1.) Explain procedural statements
2.) Write a note on task, functions and void functions.
3.) Explain advanced argument types
4.) Explain C-style argument and routine argument
5.) Explain passing argument and returning from a routine
6.) Explain time literals
7.) Explain i) Communication between testbench and DUT ii) Communication with ports
8.) Write a note on using interface to simplify connections
9.) Write a note on interface trade-offs
10.) Explain the program block and the timing region
11.) Explain driving interface through clock block
12.) Explain i) Immediate assertions ii) Customizing assertion actions iii)Concurrent assertion

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