Control Systems REVII
Control Systems REVII
REV II
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Closed-Loop Control
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Control Systems Classification
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Process Control Example
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Motion Control
Motion Control Examples
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General Control System
First Order Systems
First Order Systems
Second Order Systems
Performance Criteria
Transient Response
The poles location is the major factor for a systems’ transient response
Step Response Comparisons
Steady-State Error
Ramp
Parabola
Steady-State Error
Steady-State Error
Stability
Stability conditions
A system is stable if the real part of all poles are < 0.
TAREK A. TUTUNJI
Control Techniques / Strategies
Classical Control
Advanced Control
Intelligent Control
Root locus.
de( t )
u( t ) K p e( t ) K I e( t )dt K D
dt
Dr. Tarek A. Tutunji
PD Design Example
Analog PID Implementation
[Ref] Kilian
Digital PID Control
Analog
Digital
Tarek A. Tutunji
Digital PID Realization
Required Operations:
•Multiplication
•Addition
•Delay
Discrete PID Implementation
Digital Control Block Diagram
Classical Control: Root Locus
Discrete Systems: Pole Locations
Advanced Control
Intelligent controllers are also used when the system must make
decisions (from several alternatives) based on input data from
sensors.
w0
x1
w1
x2 f(net)
wM y
xM
M
y f xm wm
m 1
Neural Nets
Plant
Output TDL Weights
Log Log Net
+ Weights + Function Output
Plant Function
Input TDL Weights
Control Identification
ANN: Identification and Control
Intelligent Controllers Applications
Intelligent Controller Application
Analog Digital
Time variable Continuous Discrete
Time equations Differential equations Difference equations
Price
Size and Weight
Number of Digital Inputs and Outputs
Number of Analog Inputs and Outputs
Speed
Required Interrupt
Required hardware
Communication Interface
Reliability
Memory
Programming Capability
Software Support
Microcontroller
PLCs
DSPs
FPGA
PC with DAQ
y(n) x(n) * h(n) x(k)h(n k)
k -
Convolution requires:
Reflection
Shift
Multiplication
Addition
DSP Architecture Features
DSP use multiple data buses (and multiple associated address buses)
so that the processing of two signals can be done in parallel.
The address buses are also separate. This multiple bus arrangement
increases speed since instructions and data can move in parallel, and
execute simultaneously rather than sequentially.
Modified Harvard Architecture
DAGEN DAGEN
A Memory Memory B
A B
ALU
Multiplier
Shifter
Accumulators
DAGEN Memory
C Shifter
C
Instruction Pipelining
Texas Instruments.
TMS320C2000™
DSP Platform
Microchip.
dsPIC30F3010
Motorola
Custom made DSP Engines
Field Programmable Gate Arrays
FPGAs are hard-wired and the random attack of alpha rays can not
destroy/corrupt the memory areas hence collapse the device
functionality.
However, the cost is high and, therefore, they are not suitable
for a large number of products
1. Software/Firmware algorithm
On-Off, PID, Adaptive, Robust, Optimal, and Intelligent
2. Hardware system
Microcontroller, PLC, DSP, FPGA, and PC-DAQ