CS3501 CD Qb-Unit 5
CS3501 CD Qb-Unit 5
QUESTION BANK
Part -A
1. List out two properties of reducible flow graph. A/M 2012
Reducible flow graphs are special flow graphs, for which several code
optimization transformations are especially easy to perform, loops are
unambiguously defined, dominators can be easily calculated.
Data flow analysis problems can also be solved efficiently.
3. What are the uses of register and address descriptor in code generator? N/D
2012
A register descriptor keeps track of what is currently in each register.
An address descriptor keeps track of the location where the current
value of the name can be found at run time.
..
can be written as in Fig . 10.16(a) . Similarly, a
repeat-loop such as repeat
S;
unt il C
12. How would you represent the dummy blocks with no statements indicated in
global data flow analysis. M/J’2014
We say that the beginning points of the dummy blocks at the entry and exit of
a statement‟s region are the beginning and end points, respectively, of the
statement. The equations are inductive, or syntax-directed, definition of the
sets in[S], out[S], gen[S], and kill[S] for all statements S.
13. Draw DAG to represent a[i] =b[i]; a[i] = &t. N/D’2014
Page 3 of 9
14. What role does the target machine play on the code generation phase of the
compiler? A/ M
Familiarity with the target machine and its instruction set is a
prerequisite for designing a good code generator.
The target computer is a byte-addressable machine
with 4 bytes to a word. It has n general-purpose
registers, R0, R1, . . . , Rn-1.
It has two-address instructions of the form:
op source, destination
MOV (move
source to
destination)
ADD (add
source to
destination)
Page 4 of 9
t4=d*t1 t5=t3-
t4 x=t5
Assembly Code
(Target Code):
MOV e, R1
ADD f,R1
MOV b,R2
ADD c,R2
16. Write the algorithm that orders the DAG nodes for generating optimal target
code. A/ M’2015
The heuristic ordering algorithm attempts to make the evaluation of
a node immediately follow the evaluation of its leftmost argument.
The algorithm shown below produces the ordering in reverse.
Algorithm:
1. while unlisted interior nodes remain do begin
2. select an unlisted node n, all of whose parents have been listed;
3. list n;
4. while the leftmost child m of n has no unlisted parents and is not a
leaf
do begin
5. list m;
6. n:=m
e
n
d
e
n
d
PART B
(Nov/Dec 2023)
4. Explain various issues in the design of code generator. (Nov/Dec 2021)
5. Write note on simple code generator. (Nov/Dec 2021)
6. Explain in detail about Global Data flow analysis of structural programs.
(16) (Nov/Dec 2016)
7. For the flow graph shown below, write the three address code and
construct the DAG. (8)
M/J’2013
t3 = 4 *i (4) t4 = b[t2]
t5= t2 * t4
t6 = prod + t5
Page 7 of 9
prod = t6
t7 = i+1
i = t7
9. Construct DAG and three address statement for the following C Program.
N/D’2013, N/D’2014
i=1; s=0;
while(i<=10)
{
s=s+a[i][i] i=i+1;
}
10. Define a directed acyclic graph. Construct a DAG and write the sequence
of instructions for the expression a+a*(b-c)+(b-c)*d. (16)MAY/JUNE 14
Page 8 of 9
11. Explain the steps carried out for generating code from DAGs with an example.
(8) N/D’2015
12. Discuss about the following:
Copy Propagation ii) Dead-code Elimination and iii) Code
motion(6) NOV/DEC2012, MAY/JUNE 2012
13. Explain peephole optimization. (8) NOV/DEC2013 ,NOV/DEC2012,
MAY/JUNE 2012
Page 9 of 9