Chapter 1

INTRODUCTION

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1.1 Motivation
During the desktop PC design era VLSI design efforts have focused primarily on optimizing
speed to realize computationally intensive real-time functions such as video compression,
gaming, graphics etc. As a result, we have semiconductor ICs that successfully integrated
various complex signal processing modules and graphical processing units to meet our
computation and entertainment demands. While these solutions have addressed the real-time
problem, they have not addressed the increasing demand for portable operation, where mobile
phone needs to pack all this without consuming much power.

The strict limitation on power dissipation in portable electronics applications such as smart
phones and tablet computers must be met by the VLSI chip designer while still meeting the
computational requirements. While wireless devices are rapidly making their way to the
consumer electronics market, a key design constraint for portable operation namely the total
power consumption of the device must be addressed. Reducing the total power consumption
in such systems is important since it is desirable to maximize the run time with minimum
requirements on size, battery life and weight allocated to batteries. So the most important
factor to consider while designing SoC for portable devices is 'low power design'.

Another issue related to high power dissipation is reliability. With the generation of on-chip
high temperature, failure mechanisms are provoked. Among them, we cite silicon
interconnect fatigue, package related failure, electrical parameter shift, electro migration,
junction fatigue, etc.

VLSI systems rely mainly on CMOS (Complementary Metal Oxide Semiconductor). The
power dissipation in CMOS circuits is quite less as compared to its bipolar counterparts.
Secondly the dimensions of the CMOS can be scaled further which increases the density and
hence reduce the area problem. As the technology is being scaled, that is channel length is
being decreased and less area is used. With the scaling, the circuit operates at less supply
voltage and therefore power gets reduced. However, total power consumption comprises of
two factors:

1. Static Power -- This power is also termed as leakage power. Such power dissipation
occurs when the circuit is in idle state.

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2. Dynamic Power -- When the circuit is in the state of certain activity and transition from
logic ‘1’ to logic ‘0’ occurs, dynamic power dissipation occurs.

The growing market of portable (e.g., cellular phones, gaming consoles, etc.), battery-
powered electronic systems demand microelectronic circuits design with ultralow power
dissipation. As the integration, size, and complexity of the chips continue to increase, the
difficulty in providing adequate cooling might either add significant cost or limit the
functionality of the computing systems which make use of those integrated circuits. The
static or leakage power is same as or exceeds the dynamic power beyond 65nm technology
node.

1.2 Low Power Design Methodology:

Hence the techniques to reduce power dissipation are not limited to dynamic power. In this
dissertation certain circuit and logic design approaches to minimize Dynamic and Leakage
power dissipation have been discussed. Power optimization in a processor can be achieved at
various abstract levels. System/Algorithm/Architecture has a large potential for power saving
even these techniques tend to saturate as we integrate more functionality on an IC. So
optimization at Circuit and Technology level is also very important for miniaturization of
ICs. An integrated low power methodology requires optimization at all design abstraction
layers as mentioned below.

1. System: Partitioning, Voltage Scaling

2. Algorithm: Complexity, Concurrency, Regularity

3. Architecture: Parallelism, Pipelining, Redundancy, Data Encoding

4. Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing

5. Technology: Threshold Reduction, Multi threshold Devices.

Dynamic power varies as Vdd2. So reducing the supply voltage reduces power dissipation.
Also selective frequency reduction technique can be used to reduce dynamic power. Multi
threshold voltage can be used to reduce leakage power at system level. Transistor resizing
can be used to speed-up circuit and reduce power. Parallelism and pipelining in system
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architecture can reduce power significantly. Clock gating, reversible logic are certain other
techniques to lower the power dissipation.

Ideally leakage power does not contribute towards total power dissipation. As the technology
is decreased, leakage power has become a major contributing factor towards the power
dissipation. The leakage current has various components and each leakage current component
dominate at different situation. These leakage currents in deep micron technology result in
excessive power dissipation in memory arrays or more specifically in the microprocessors.
High speed memory caches form significant part of memory array.

Power consumption has become an important limitation in the portable devices such as
mobile phones and laptops. If power dissipation increases, more battery backup would be
needed or continuous charging would be required. So designing of the devices have to be
done in such a manner that power consumption both in active as well as standby mode is
reduced.

Memory array consists of an array of memory cell. Each cell stores a single bit of data either
a logic ‘1’ or logic ‘0’. Combination of these cells in rows and columns form a memory
array. Various types of memory are available in the market. These memories have been
named in the figure 1 below.

Figure 1.1: Types of Memory Devices

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RAM stands for Random Access Memory. RAM is of two types: Static RAM and Dynamic
RAM. Static random-access memory (SRAM) is a type of semiconductor memory that uses
bistable latching circuitry to store each bit. SRAM do not require refreshing periodically. But
the circuit is volatile that is loses its content when the power is switched off.

The symmetric structure of SRAMs also allows for differential signalling, which makes
small voltage swings more easily detectable. Another difference with DRAM that
contributes to making SRAM faster is that commercial chips accept all address bits at a time.

SRAM cell can be designed using either transistor or MOSFET. MOSFET type SRAM’s are
preferred these days. Depending upon whether clock is applied or not, the memory cell could
be synchronous type or of asynchronous type. In case of synchronous SRAM’s the
operations are performed on the clock event. In asynchronous one, the extra control signals
are used to read and write in the cell.

1.3 Objective:

Since the leakage current is increasing with the scaling of devices, it should be minimised.
Application of leakage reduction technique is done in such a way that stability of the device
must be maintained. The main objective of dissertation is to reduce leakage power in 5T, 6T,
7T SRAM and check the stability of the circuits while employing these schemes. Secondly,
work aims to study the variation of power in active mode. All three configurations of SRAM
cell shall be analysed and compared in terms of read power, write power and hold current.
The variation of hold current at different temperatures will also be tested. The graphs of
SNM for the conventional and proposed circuits shall be analysed.

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 1.4 Outline of the thesis:

Chapter 1 gives a brief overview regarding the need to reduce leakage current. The types of
memory arrays used are also explained briefly. This chapter explains the need of low power
and its importance in portable devices.

Chapter 2 describes the basic concepts regarding the memory structure and various
configurations of memory cell have also been explained. Secondly the concept of stability of
the cells has also been explained along with its variation with scaling.

Chapter 3 provides an overview of various factors affecting the leakage current and certain
techniques to overcome leakage current. Certain techniques employed in the SRAM cells to
reduce leakage have also been discussed.

Chapter 4 shows the simulation results of the circuit level techniques employed on 5T, 6T
and 7T SRAM cells and various parameters have been compared. The SNM of conventional
and proposed circuit has been compared and analysed.

Chapter 5 concludes the thesis and a brief summary of the results have been discussed. The
future scope is also presented in this chapter.

Chapter 6 for the implementation of the circuits and to have an idea regarding the basic
concept of the circuit, various research papers has been studied. This chapter provide
references to these papers.

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 Chapter 2

Memory array structure

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The memory array consists of various cells arranged in the form of rows and columns. The
size of the memory array is N* M bits. Here N is the number of horizontal rows and each row
store M bits. M bits are stored in M cells. Each cell may have different configuration such 1T,
4T, 5T and many more. Here T represents the transistor and numerical value ahead of T
represents the number of transistors used in design of the SRAM cell.

2.1 Extra circuitry involved

For normal working of memory array, certain extra circuits are added while designing. These
circuits include sense amplifier, pre charge and equalization circuit, address decoder. These
circuits have been explained below along with their circuits.

2.1.1 Sense Amplifier

Read operation involves pre charging of both bit lines and depending upon the value stored in
the cell, one of the bit lines is discharged. These bit lines have large capacitance due to large
number of access transistors connected to them. Thus charging and discharging of the bit
lines take considerable amount of time and hence read operation can be regarded as slower
operation. Sense amplifier detects the differential voltage on both the bit lines and generates
full voltage swing. The circuit diagram of sense amplifier is drawn below in the Fig. 2.1.

Vdd

BLB
BL

SAE

Figure 2.1: Sense amplifier circuit

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The operation of sense amplifier has to properly timed so that correct outputs are obtained.
The sense amplifier becomes on when Sense Amplifier Enable (SAE) signal is active high. If
the sense amplifier circuitry is activated even before proper differential voltages are
developed on the bit lines then it will not be able to properly resolve the output. In case if the
sense amplifier is activated after generation of proper differential output, then read time
would increase and make the system slower.

2.1.2 Pre charge and Equalization Circuitry

Before the read operation bit lines are pre charged to certain specified value. In general, the
bit lines are pre charged to Vdd, Vdd-Vth or Vdd/2. Once charged these bit lines remain in
floating state. In memory array, pre charging before read operation is done by pre charge and
equalization circuit. The circuit diagram is shown in figure 2.2.

Figure 2.2: Pre charge and Equalization circuit

Three PMOS transistors are connected in the manner showed in figure 2.2. Signal ‘Pre
charge’ is used to turn on or off the pre charge circuit. It can be seen that if pre charge signal
is active low, then BL and BLB both remain at V dd. Basically the rotated PMOS (connected
to both BL and BLB in figure) is used for equalization purposes. If this transistor is not used,
condition may arise that both the bit lines are not pre charged to a single voltage level instead
different voltages are obtained on the complementary bit lines. Charging of bit lines to two
different voltage levels lead to incorrect results. Once charged, these bit lines will remain in
floating state. Read operation would be performed after pre charge phase by asserting word
line. Two separate pre charge and equalization circuit are used. One is used for sense
amplifier and other for bit cell column. This is done so that sense amplifier is isolated from
the circuit and a complete voltage swing is generated at the output.
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2.1.3 Address Decoder:

Address decoders are used to select a particular row or column. The address given is of the K
bits. The data is stored in N horizontal rows each containing M bits of data. The address
decoder takes K bit of address and uses it to select one of the horizontal rows. The relation
between the number of rows and address bits is given as N = 2 K. Bit lines are used to select a
particular column and word line is used to select a particular row.

Once a row is selected the data can be written to the cell or read from the cell. Intersection of
the selected row and column leads to memory cell selection. Address decoder basically
decodes the address and corresponding cell is activated for read and write operation.

Let us suppose that we wish to write in the last cell of the first row. Then word line of
corresponding row that is first row will be activated. Each column is associated with the pair
of complementary bit lines as shown in the figure 2.3. The bit lines of fourth row will be
activated. Hence the data either logic 0 or logic 1 can be written into the required cell. Once
the data is written, for hold state word line is de activated and both the bit lines are asserted.
The arrangement of memory cell in the array is shown in the diagram below:

Figure 2.3: Memory Array

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2.1.4 Timing circuitry:

The timing control block is a critical component in any SRAM design. It is responsible for
generating all of the internal signals for the correct read and write operation of the SRAM.
These signals include control for the pre charge, word line, sense amplifier clocking and write
driver activation. Several SRAM cell failure mechanisms are heavily influenced by the cell's
control signal timing. These failures have been explained below:

1. Operational failure:

2. Stability Related:

3. Power Related:

Since a read is the slowest memory operation, its timing is the most vulnerable to failure.
During a read operation, the amount of differential voltage generated on the bit lines is
directly proportional to two parameters:

 The width of the word line signal

 Strength of the SRAM cell.

The width of the word line signal is a function of the timing block design. Width here refers
to time period for which WL signal is high. However, the strength of the SRAM cell is a
function of process, process variability, aging degradation and the cell design. The stability of
the SRAM cell is affected by the increase in variability and by the decrease in supply voltage.
The term SNM that is Static Noise Margin determines the stability of the cell. SNM is the
amount of voltage noise required at the output nodes to flip the state of the cell. For a cell to
be stable SNM should have a high value. Stability is needed to be defined for read, write and
hold operation.

Changing the SRAM control timing can have a large effect on the power dissipation of an
SRAM. This is especially true during a read operation. It is common for SRAM arrays to
operate on lower supply voltages to reduce power, especially leakage power. But lower
supply voltage requires more access time to generate proper differential voltage on the bit
lines, resulting in more power dissipation. This is called as power failure. Each rectangular

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block in the figure represents the memory cell of 1 bit. The line connecting each cell from
upper direction is word line. And two lines joint to the cell sideways are the complementary
bit line pair. Here each cell stores single bit of data and the each cell have different structure.
Each structure has been explained below.

2.2 6 T SRAM Cell

The conventional 6T SRAM cell comprises of 6 transistors, two pair of cross coupled
inverters and two access transistors. The cell is symmetrical in nature. With the help of access
transistors, the data inside the cell can be read. Write operation too is performed using these
transistors only. The word line and the bit lines are referred to as row selector and column
selector respectively. The circuit diagram of 6T SRAM cell is as shown in figure 2.4:

Figure2.4: Conventional 6T SRAM cell

Here ‘WL’ represents Word line and ‘BL’ represents bit line and its complement is
represented as ‘BLB’ that is bit line bar. ‘X’ and ‘Y’ are internal storage nodes. P1 and P2 are
two pull up transistor and N1 and N2 are two pull down transistors. N3, N4 are referred to
access transistors or pass transistors because these two transistors provide access to the
internal storage nodes. Each cell can perform three operations:

I. Read operation

II. Write operation

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III. Hold State

Read Operation: The read operation starts by charging both the bit lines to logic ‘1’ and de-
asserting the word line (WL). Then the word line is activated and bit lines remain in floating
state. Now if at node ‘X’ logic ‘1’ and at node ‘Y’ logic ‘0’ is stored, then P1 and N2 will get
on and P2 and N1 will remain off. The BLB would get discharged to ground through
transistors N4 and N2. Similarly if logic 0 is stored in the cell, BLB would remain at high
logic, whereas BL would be discharged through N3 and N1.

Write Operation: The data to be written in the cell is applied to the bit line (BL) and it’s
complement to BLB. Word line is asserted and the strength of the access transistors should be
strong enough to properly write the data into the cell. If data to be written is logic 1, then bit
line is provided with the high logic and bit line bar with logic 0 or lower logic. Now since
WL is activated, the data through complementary bit lines would be transferred the
corresponding nodes and data would be written.

Hold State: When no operation is being performed in the cell, the cell is in the hold state or
standby mode. WL is de asserted and the state of the cell remains as it is. The cell should be
stable in the hold state. It should not flip states. That is if at node X logic 1 is stored, then in
hold operation, this node should not be discharged to logic 0.

2.3 7T SRAM CELL

The 6 T cell suffers from certain stability issues due to its symmetrical structure [2]. The
easier it is to write the data in the cell more difficult it would become to read the data. For
read to be proper, the access transistors should be weak, but for write operation they should
have high strength. Extra signals are required for the proper operation of 7T SRAM cell. The
area occupied by the 7T cell is more as compared to the 6T cell because of the extra
transistor. So, here we discuss non symmetrical 7T SRAM cell. The circuit diagram of the
cell is given below:

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 Figure 2.5: Conventional 7T SRAM cell [3]

Read operation: Before start of read operation BL_bar and BL both are pre charged by
keeping WL and R at zero logic. Then the bit lines are allowed to float and simultaneously
the WL and R are provided with the logic 1. Suppose at node ‘Q’ logic ‘0’ is stored, then BL
is discharged via N4 and N2 and BL_bar will be pulled up to logic 1. If ‘1’ is stored at node
‘Q’ BL_bar is discharged via N3, N5 and N1. All the three transistors get on when logic 1 is
present at Q. BL remains at logic 1.

Write operation: For performing write operation, WL signal is high and R and W signals
both are at logic low. Since the structure of cell is in such a way that Q node is the output of
Q2, so inverted data would be stored because of inverter action of P2 and N2. Similarly with
the help of N1 and P1 complement data would be stored at node Q_bar.

Hold Operation: During hold operation, both bit lines are pre charged high and WL is de
asserted. The cell is not in operating mode and the special care has to be kept so that data in
the cell do not flip. Transistor sizing must be done in proper way so as to avoid flipping of
data stored in the cell.

2.4 5T SRAM CELL

With the advancement in technology, reduced chip area and hence increased density has
become a prime concern. So 5T cell was proposed [4]. This cell makes use of single bit line
as compared to two bit lines in above two cases. Moreover as the name suggests one less
transistor is used in comparison to 6 T cell. A special pre charge requirement is also present
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in this cell. Generally the pre charge voltage for the above cases is either V dd or Vdd/2. But in
this case a proper pre charge voltage is required, else the cell will not operate properly. For
the generation of this pre charge voltage, an extra supply voltage or a separate on chip dc to
dc converter is needed. The difference between 5T and 6T is that 5T consists of single bit line
and the output has to be sensed differentially. So the whole memory is divided into two parts.
The bit line of one part and bit line of the other part of the memory act as the differential pair
to the sense amplifier. Hence the output of the memory cell can be resolved by the sense
amplifier. The cell occupies less area than 6T and 7T cells. The circuit diagram of the cell is
shown below in figure 2.6.

Figure 2.6: Conventional 5T SRAM Cell

Here the only bit line used is BL and WL represent the word line. The operation of the cell is
same as the 6T cell. But in this case pre charge voltage of 0.6 volt is required for proper read
and write. Since the memory devices are mainly used in the microprocessors where different
supply voltages are required, so generation of extra pre charge voltage will not pose a greater
problem. The transistor sizing must be kept in mind and the sizes in the diagram correspond
to 180 nanometre technology. No complementary node is present in the single cell so the
node from the other cell acts as the complementary node for the selected cell. Smaller M5
would result in less area consumption and would increase the write stability of the cell.

Read Operation: The single bit line is pre charged to 0.6 V. WL is de asserted initially. The
bit line is kept floating at pre charge voltage and after that word line is made active high. If
the data to be written is logic 0, then the bit line is discharged. Else the bit line is pulled up to
Vdd. The cell must be sized in a accurate manner so that the cell does not flip state while
reading the data stored in the cell.

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Write Operation: The write operation of 5T SRAM is similar to write operation of 6T
SRAM cell. The bit line is provided with the data to be stored. If 1 is to be stored, transistor
M2 will become on. The output of the inverter pair (M4 and M2) is 0 which would be stored
at the other node. Similarly if 0 is to be stored, the corresponding node will store logic 0, and
this node act as the input to the other inverter pair (M4 and M2). Its complement value that is
logic 1, is stored in the other node.

Hold operation: To hold data, WL is de asserted. The states or the data should not flip. The
data in the memory cell must remain as it is. The values stored at the node should not get
changed.

2.5 Stability

The sizing of transistors must be done in such a way that the cell remains stable. The stability
of the cell is defined in terms of static noise margin (SNM) [5]. It is the maximum supply
voltage that can be given to the cell such that the cell does not flip its state. The static noise
margin decreases with the supply voltage and technology scaling [6]. Process variation and
temperature also play a crucial role in determining the noise margin of the cell. When the
supply voltage is reduced, the power consumption reduces but stability of the cell gets
affected. The schematic for calculation of SNM is shown below:

Figure 2.7: Schematic for calculating SNM [6]

The two DC noise sources ‘Vn’ operate simultaneously on the cross coupled inverter pair.
Here inv1 and inv2 represents two cross coupled inverters. VL and VR are two storage nodes.
The curve obtained is referred to as butterfly curve. The side of the largest square that can be
fitted into that curve corresponds to the noise margin. The figure 2.8 shows the butterfly
curve.
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 VL

VR

Figure 2.8: Butterfly curve showing largest square that can be fitted

The curve basically is obtained by superimposing the voltage transfer characteristics of two
cross coupled inverters. First the one noise source is made to sweep from 0 volt to V dd. The
output is measured from the output terminal of the same inverter. The same procedure is
applied to obtain the input output characteristics of the other inverter. Once both the
characteristics are obtained, they are superimposed upon each other to get the required graph.
A square is embedded into the curve and the value of side gives the accurate value of noise
margin. The value of the noise margin should be high. The test set up for calculation of SNM
is shown below in the figure 2.9.

Figure 2.9: Test setup for calculating SNM [7]

SNM curves can be obtained for all the three operations. For calculating read margin, both
the bit lines are clamped to Vdd and WL is also asserted. For hold state, the bit lines are pre
charged and word line is de asserted.

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 Vdd

VL

2/3 Vdd

VR

Figure 2.10: Variation of SNM with supply voltage

When operated in read mode, the cell is weakest and has the lowest value of noise margin [8].
With the scaling of Vdd, the noise margin gets reduced. From figure 2.10 it can be seen that
as we reduce the supply voltage static noise margin gets reduced. When the supply voltage is
Vdd, the square that can be fitted inside the butterfly curve is larger whereas when the voltage
is reduced to 2/3 times of V dd, the size of the square is reducing. So reduction of the supply
voltage, beyond certain limit will lead to unstable memory cell. Although the power of the
cell gets reduced, when we apply less voltage but stability of the cell is affected. For the
proper operation of the memory array, the cell should be stable. Many leakage reduction
techniques have been proposed till date. All these techniques do try to reduce the power
dissipation but the stability might get affected. So, special consideration must be given to the
stability issue.

In the next chapter, various factors contributing the leakage current and measures to avoid
this current is discussed. A brief overview of all the circuit and process level techniques to
reduce leakage current is discussed. Certain techniques which have been employed in the past
to reduce leakage have been discussed in the next chapter.

18
 CHAPTER 3

LITERATURE
SURVEY

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The scaling of technology that is reduction in the channel length, leads to various effects.
These effects play an important role in increasing the leakage current. Scaling of devices lead
to higher density. The power supply for obtaining the optimized result too reduces thereby
decreasing the power consumption. But decreasing the voltage supply implies that the
threshold voltage of the device too shall get scaled. The sub threshold leakage current and
threshold voltage have inverse relation among them. The sub threshold leakage current
increases with the decrease in threshold voltage [9]. The variations arising due to the decrease
in the threshold voltage hence increase leakage current is referred to as short channel effects
(SCE).

In deep sub micrometre technology, apart from sub threshold conduction various others
leakage currents do contribute towards the total power dissipation. These currents have been
briefly explained in the following sections.

Gate

Source I4 Drain

n+ I2 n+

I6 P well I3 I5 I1

Well

Figure 3.1: Leakage current components

Figure 3.1 shows various leakage components that flow inside the MOS transistor. The
diagram corresponds to the NMOS transistor with p type well and source and drain of n type.
Here the leakage currents are described as:

I1: Reverse bias PN junction leakage current

I2: Sub threshold leakage current

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I3: Oxide tunnelling current

I4: Gate current due to hot carrier injection

I5: Gate Induced Drain Lowering (GIDL)

I6: Channel Punch Through

I2, I5 and I6 dominate when the device is in off state. I1 and I3 flows both in off and on
state. I4 occurs mainly in off state but mainly during the transition. These currents are briefly
explained in the following section.

3.1 Leakage Current Components

Various leakage current components have been explained in the following section.
Each component has different effect on the scaling of device geometry. The variation of
leakage current with temperature as well as with other factors is briefly explained below.

3.1.1 PN Junction Reverse Bias Leakage Current ( I1 ):

For the proper operation of MOS transistors, drain and source region are reversed
biased with respect to substrate. That is in case of NMOS transistors the substrate is
connected to ground so that substrate being of P type is connected to more negative terminal
as compared to the source terminal. Hence the minority current will flow from source region
to substrate. But due to shortening of the channel length the reverse bias leakage current is
increasing. Reverse bias current is dependent on the junction area and on the concentration of
impurity added [10].

Band to Band Tunnelling plays a crucial role when the device is heavily doped and
contributes towards PN leakage current [11]. High electric field across the reverse bias
junction causes charge carriers to flow from valence band of P region to the conduction band
of N region. The diagram 3.2 below explains the mechanism of band to band tunnelling. Ec
represents the conduction band and Ev represents the valence band. The electrons move from
valence band of the P side to the conduction band of N side.

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 Ec qVbi

Ev qVapp
Ec
P side Ev
N side
Figure 3.2: Band to Band Tunnelling

3.1.2 Sub Threshold Leakage Current (I2) :

When the gate to source voltage of the MOS transistor is less than threshold voltage,
it is assumed that no current would flow. But due to the presence of inversion layer certain
current flows. This current is called as sub threshold leakage current and has exponential
dependence on the gate to source voltage (Vgs). This region is referred to as sub threshold
region. The sub threshold current is given as:

Id = I0 e(Vgs / ζVt) (1)

Equation 1 clearly shows that drain current varies exponentially with V gs. Here Vt represents
threshold voltage. Id is the drain current and ζ is nonideality factor. As the threshold voltage
decreases, the leakage current would increase. So to minimise the sub threshold current, the
threshold voltage must increase which actually is increasing due to scaling of devices and
supply voltage. At room temperature Vgs must decrease by 80 mv for 1 decade reduction in
Id. The variation of threshold voltage with the Vgs can be explained with the help of figure
3.3 below.

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 Figure 3.3: Characteristics of MOS transistor in sub threshold region

The sub threshold leakage current or more specifically threshold voltage is dependent on
various factors. These factors are briefly explained below.

1. In the short channel devices, the threshold voltage is dependent on the drain potential
and the channel length. Thus the sub threshold current varies with the drain bias. This
effect is referred to as Drain Induced Barrier Lowering (DIBL). Application of high
drain voltage leads to the decrease in barrier height and hence threshold voltage
decreases. Thereby increasing the sub threshold leakage current. Higher surface and
channel doping and shallow source/drain junction depths reduce the DIBL effect on
the sub threshold leakage current [12], [13].

2. Reverse biasing source in regard to the substrate increases the bulk depletion region
and threshold voltage [14]. Basically reverse biasing the substrate with respect to
source increases the value of Vsb. In case of NMOS transistor the body is of P type
and if both source and body are connected to same potential V sb becomes zero.
However if substrate is provided with negative potential that is value of V b is less than
zero then value of Vsb shall increase.

Vth = Vth0 + γ ( ( 2φf + Vsb) - 2φf ) (2)

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 According to equation (2) increase in the value of V sb will lead to increase in the
threshold voltage and hence reducing the sub threshold leakage current. Here φ f is the
work function of the silicon substrate.

3. The threshold voltage of the device varies with the channel length. This variation of
Vth with channel length is referred to as V th roll off. Due to 2 dimensional field
patterns in short channel device which arise because of the close proximity of source
and drain region, Vth reduces. Reduction in Vth results in increase of sub threshold
current. It can be seen from figure 3.4 that V th reduction is more prominent at higher
drain bias. The dotted lines show the variation of threshold voltage at higher drain
potential. It can be observed that threshold voltage decreases more rapidly when the
drain potential is high as compared to the case when the drain potential has less value.

Figure 3.4: Variation of channel length with Vth

4. The operating temperature of the device too plays a crucial role in varying the
threshold voltage. In VLSI circuits, the temperature at which the device is operated, is
quite high. So the variation of threshold voltage with the temperature needs to be
monitored. In 35 nanometre technology, the slope of the sub threshold current graph
varies from 58.9 mV to 81.9 mV per decade when temperature is raised from -50°C to
25°C [15]. When the temperature is raised, the slope of sub threshold characteristics
increases and the threshold voltage decreases thereby increasing leakage current. So
the above said reasons are the main contributing factors towards the increase of sub
threshold leakage current. This current is also called as I off as the current dominates
when the device is in off state.
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3.1.3 Oxide tunnelling Current (I3):

The main cause for this current is the reduction in the thickness of gate oxide. Thin gate
oxide results in the establishment of stronger electric field. This electric field along with the
thin oxide results in tunnelling of charge carriers from gate to substrate and vice versa. There
are two mechanisms by which tunnelling may occur. These are:

1. Fowler–Nordheim (FN) tunnelling

2. Direct tunnelling

In the case of FN tunnelling, electrons tunnel through a triangular potential barrier, whereas
in the case of direct tunnelling, electrons tunnel through a trapezoidal potential barrier. The
tunnelling probability of an electron depends on the thickness of the barrier, the barrier
height, and the structure of the barrier. Therefore, the tunnelling probabilities of a single
electron in FN tunnelling and direct tunnelling are different, resulting in different tunnelling
currents.

3.1.4 Injection of Hot Carriers from Substrate to Gate Oxide (I4):

As it has been explained that due to short channel and high electric field charge
carriers either electrons or holes gain quite high energy to overcome the interface potential
and enter into the oxide layer. This phenomenon is referred as hot carrier injection. Electrons
are more likely to undergo this process because the barrier height for electrons is less and the
mass of the electrons is less than that of the holes [16].

3.1.4 Gate-Induced Drain Leakage (I5) :

When the gate is biased to form an accumulation layer at the silicon surface, the
silicon surface under the gate has almost same potential as the p-type substrate. The silicon
surface behaves more like a p type material because of the presence of accumulated holes.
Thus as a result the depletion width gets reduced. This reduction in the depletion width
causes the crowding of electric field hence increasing its value [17]. The substrate is at lower
potential for minority carriers, the minority carriers that have been accumulated or formed at
the drain depletion region underneath the gate are swept laterally to the substrate, completing
a path for the GIDL [18]. Thinner oxide thickness and higher supply voltage enhance the

25
electric field and therefore increase GIDL. This phenomenon is more pronounced at moderate
doping levels where both the electric field and depletion width is considerable.

3.1.5 Punch through (I6):

In short-channel devices, due to the proximity of the drain and the source, the
depletion regions at the drain-substrate and source-substrate junctions extend into the
channel. On scaling the device and keeping the doping concentration constant, the distance
between the depletion region of source and drain decreases. For the normal operation of MOS
transistor drain voltage too is applied. Combination of both these factors that is reduction of
channel length and application of drain voltage leads to the merging of the depletion region.
This process is called punch through. An increase in the drain voltage beyond the value
required to establish the punch through lowers the potential barrier for the majority carriers in
the source. Thus, more of these carriers cross the energy barrier and enter into the substrate,
and the drain collects some of them. This results in the increase in sub threshold current.

3.2 Sources of power dissipation

There are three sources of power dissipation in a digital complementary metal oxide
semiconductor (CMOS) circuit.

The first source is logic transitions. As the “nodes” in a digital CMOS circuit transits
again and again between logic 1 and logic 0, the parasitic capacitances are charged and
discharged. Current flows through the channel resistances of the transistors, and electrical
energy is converted into heat and dissipated away. This component of power dissipation is
proportional to the supply voltage, node voltage swing and the average switched capacitance
per cycle. The dissipation due to transitions varies overall as the square of the supply voltage.
The dynamic power is given as:

Pdynamic = α C Vdd2 (3)

Equation 3 corresponds to the dynamic power dissipation. Here P dynamic represents the
dynamic power dissipation. α is the activity factor. It basically determines the frequency of
transition from 1to 0 and vice versa. C represents the total capacitance of the circuit and V dd
is the supply voltage. If we reduce the supply voltage, power dissipation gets reduced by the

26
factor of 4. So the scaling is done so as to reduce the voltage supply and hence the power
consumption.

Short-circuit current that flows directly from supply to ground when n-sub network
and p-sub network of a CMOS gate both conduct simultaneously are the second source of
power dissipation. With input(s) to the gate stable at either logic level, only one of the two
sub networks conduct and no short-circuit current flow, but when the output of the gate is
changing in response to change in input(s), both sub networks conduct simultaneously for a
brief interval. The duration of the interval depends on the input and the output transition (rise
or fall) times and so does the short-circuit dissipation.

Leakage Power consumption occurs when the device is in the off state still the current
flows in the circuit due to minority charge carriers. The contributing factors have been
explained in the section 3.1 above. When the device is in off state, ideally no current should
flow in the circuit. Consider a basic 6T SRAM cell, in which even in the active state a pair of
cross coupled transistors shall always remain off. So even in the active state power
consumption shall get reduced if certain leakage reduction is applied. Due to the scaling of
the devices the leakage current has become a considerable component of the power
dissipation and hence can’t be neglected. So, certain techniques must be employed so as to
reduce the total power dissipation of the circuit.

3.3 Leakage Current reduction Techniques:

There are various process level as well as circuit level techniques that can be utilized
to reduce the power dissipation due to leakage currents. At circuit level the power dissipation
can be reduced by controlling the voltage levels at various terminals of the device. And in the
process level dimensions, doping levels are taken in consideration. Mainly these techniques
strive to reduce the sub threshold leakage current but some of them can reduce other leakage
currents too. Depending upon the technology used, the leakage current dominates. Certain
circuit level techniques have been explained in the following sections.

27
3.3.1 Leakage Control Using Transistor Stacks:

The stacking effect is based on the concept that when more than one transistor connected in
series are in the off state, the sub threshold leakage current gets reduced. This concept has
been explained below taking an example of two off NMOS transistors.

M1

M2

Figure 3.5: NMOS transistors connected in series

Let us assume that initially on upper NMOS transistor M1 is in off state. Then the source
terminal would be connected to the ground and the source and body potential would be same.
When both A and B are equal to zero, both the transistors would become off. But now when
an extra NMOS transistor M2 is connected to the source terminal of M1, then certain positive
voltage must be present at point M. Due to this positive potential at M, source to body
potential becomes positive as the body is connected to the ground that is zero potential and
the source is connected to some positive potential. Then according to the equation 2,
threshold voltage increases. Increasing the threshold voltage, results in the reduction of the
sub threshold current.

3.3.2 Multiple Vth Design:

As the name suggests multiple threshold voltage transistors are used in a single chip. Both the
low and high threshold devices have their own weakness and strength. The devices with high
threshold voltage can suppress the sub threshold leakage current and the low sub threshold

28
devices improve the performance [18]. Multiple threshold voltages can be obtained by the
following techniques:

1. Multiple Channel Doping:

Multiple-threshold voltages can be achieved by adjusting the channel-doping

densities. Figure 3.6 show the variation of channel doping density with the threshold
voltage [19]. As the doping concentration increases the threshold voltage too
increases.

Figure 3.6: Variation of threshold voltage with doping concentration

2. Multiple Oxide CMOS:

Two different gate oxide thickness can be used to vary the threshold voltage. Dual
threshold voltage device can be obtained by depositing different layer of oxide on the
transistor. For transistors having a higher oxide thickness result in a high threshold
voltage, and hence low sub threshold leakage. On the other hand, lower oxide thickness,
and hence lower threshold voltage, maintains the performance. The devices with the
higher oxide thickness are used in noncritical paths whereas the devices with lower oxide
thickness are used in critical paths. Higher oxide thickness leads to the reduction of gate
tunnelling current as the charge carriers won’t be able to tunnel through the thick gate
oxide. As the technology is being scaled higher oxide thickness produces adverse effect

29
on the SCE’s. So to avoid this condition, aspect ratio of the device must be decided in
appropriate manner.

3. Multiple Body Bias :

If for the all NMOS transistors, different wells are used while fabrication, varied
threshold voltage can be obtained. The bodies of these well shall be biased differently that
is with different potentials.

3.3.3 Dynamic Threshold Voltage Designs:

Dynamic threshold voltage scaling is a technique for active leakage power reduction. This
scheme utilizes dynamic adjustment of frequency control depending on the workload of a
system. When the workload decreases, less power is consumed by increasing threshold
voltage. Various varieties of dynamic threshold designs have already been proposed [19],
[20]. In of the scheme described in [19] the software is programmed in such a way that it
switches the control from Vth high to Vth low according to the state in which the device is
operating.

In [20] a feedback circuit controls the variation of threshold voltage. The device operates
according to certain reference frequency and the body of the NMOS and PMOS
transistors is biased accordingly. The error signal generated help to properly and
dynamically bias the bodies of respective MOS transistors. Hence the power dissipation
can be varied dynamically be changing the threshold voltages.

3.3.4 Supply Voltage Scaling:

Scaling the voltage supply reduces the power dissipation according to the equation 3. But
reducing the supply voltage slows down the operating speed of the devices. So it’s not
advisable to scale the supply voltage in all the states of operation. It is mostly preferred to
operate the transistor at the optimized voltage under the active state and to scale down the
supply voltage in the standby mode. The concept of dynamic voltage scaling is dominant
in the voltage scaling. In this scheme, the voltage is scaled according to the mode of

30
 operation. The supply voltage is divided into many voltage levels. Each voltage level is
associated with certain fixed frequency value. If we reduce both the supply voltage and
the frequency, the performance shall degrade. Various techniques employing this concept
are explained below:

(a) Data retention gated-ground cache: A data retention gated-ground cache (DRG
Cache) puts the unused portions of the memory core to low leakage mode to reduce
power. An extra NMOS transistor is introduced in the leakage path from the supply
voltage to the ground of the static random access memory (SRAM) cells. The extra
transistor is turned on in the used sections and off in the unused sections, essentially
“gating” the supply voltage of the cells. Since two transistors get off simultaneously
due to stacking effect, the power reduces. While the gated-ground transistor must be
made large enough to sink the current flowing through the SRAM cells during active
mode and to enhance the data retention capability of the cache in the standby mode, a
large gated-ground transistor may reduce the stacking effect, thereby diminishing the
energy savings.

Figure 3.7: Gated Cache

Conventional SRAM stores the data as long as the power supply is on. This is because the
cell storage nodes, which are at zero and one, are firmly strapped to the power rails through
conducting devices (by a pull down NMOS in one inverter and a pull-up PMOS in the other
inverter). When the gated-ground transistor is ON, the DRG cache behaves exactly like a

31
conventional SRAM in terms of data storage. Turning off the lower NMOS transistor cuts off
the leakage path to the ground.

(a) Drowsy Cache: In drowsy cache mechanism, switching between two different
supply voltages is done. The access transistors and the transistors needed for
switching are of high threshold voltage. This technique gives the combined
effect of scaling the supply voltage as well as leakage reduction [21]. Basically
leakage reduction is done by varying the threshold voltage.

Figure 3.8: Drowsy cache implementation

All the techniques described above are used for leakage reduction. Certain techniques have
already been implemented in the memory circuits. Depending upon these techniques certain
circuit designs have been described. In the multiple threshold scheme, the design such as
MTCMOS, variable threshold CMOS, dynamic threshold CMOS are there. In MTCMOS the
high threshold transistor is connected in series to low threshold circuitry. A PMOS or NMOS
transistor can be used. A PMOS is connected between the supply voltage and the circuit.
Depending upon the control signal connected to its gate, the transistor shall remain on or off.
Similarly a NMOS circuit is connected between the circuit and the ground. This creates a sort
of virtual ground. This circuit shall reduce the leakage power only in the standby mode not in
the active mode.

32
 3.4 Previous Leakage reduction techniques employed on SRAM cell

Various techniques have already been proposed for leakage reduction in SRAM cells. Some
of the techniques are described below. In [22] the threshold voltage and oxide thickness of
certain transistors in 6T SRAM cell has been changed. Corresponding to each configuration
the leakage power has been calculated. The technique used employed was if the threshold
voltage of the transistor is increased the sub threshold leakage current would reduce.
Similarly if the thickness of the oxide is varied, the leakage current change. On increasing the
oxide thickness, the leakage current reduces. Various circuit configurations proposed in [22]
are given in the figure 3.9.

Figure 3.9: Hybrid SRAM cell

33
Here C1 to C5 represent various hybrid configurations. By applying this reported technique
to a 64Kb SRAM in 65nm technology node, the total leakage power dissipation of the SRAM
has been reduced by 53.5%. The concept of gated V dd has also been implemented in [23].
The results indicated that a wide NMOS dual-V t gated- Vdd with a charge pump reduces
leakage most with minimal impact on cell speed and area. In this paper, the technique of dual
threshold as well as gated Vdd both was employed. Here instead of PMOS, NMOS was
employed for gating the supply voltage.

The concept of MT-CMOS has been employed on both 5T as well as 6T SRAM cell in [24].
The paper compares this technique with the various other techniques such as gated V dd,
dynamic scaling and conventional one. The paper concluded that concept of MT-CMOS was
more effective in the 5T SRAM cell whereas in 6T gated V dd led to more reduction in leakage
power.

In [25], the concept of dual threshold voltage has been introduced. Depending upon the
transistors where the increased threshold voltage is employed, the cell may be asymmetric or
symmetric. The asymmetric cell is shown in figure 3.10.

Figure 3.10: Asymmetric 6T SRAM cell

A technique to increase the ground voltage during the inactive state is proposed in [26]. In
this scheme, during the hold or standby mode of the cell, the circuit below the cell gets

34
activated and the ground voltage level is raised. The switch provides 0 Volt at the ground
node during the active mode and a raised ground level (virtual ground) during the inactive
mode. An increase in virtual ground voltage reduces the gate-source and gate-drain voltage of
transistor M1 and also the gate drain voltage of transistor M2, which results in a sharp
reduction in gate leakage currents of these two transistors. The circuit diagram of the reported
circuit is given in the figure 3.11. The circuit comes in the active mode when value of clk is 1
and the standby mode is activated when the clk =0. The circuit below the SRAM cell is called
as AVL circuit that is Adaptive Voltage Level circuit.

Figure 3.11: SRAM cell with AVL control circuit

This AVL circuit can be employed either in the upper half of the cell or in the lower half.
This circuit was successful in reducing all the leakage currents except the gate leakage
currents.

35
.

Chapter 4

Simulation Results

36
4.1 Simulation Results of 6T SRAM cell

This section depicts the simulation results of the work done on 6T, 7T and 5T SRAM cell.
The software used is Design Architect by Mentor Graphics. All the result has been simulated
on 180 nanometre technology. Since the technology used is 180nm for obtaining the
optimized results, voltage supply of 1.8V is used. WL in the circuit is word line. BL is the bit
line and BLB is the bit line bar. Q and QB are two storage nodes.

The figure 4.1 below shows the circuit diagram of conventional 6T SRAM cell. The two
transistors on the top are two PMOS whose substrate terminal is connected to the supply
voltage or to the highest positive supply in the circuit. The two transistors on the left and right
are NMOS pass transistors whose drain terminals are connected to BL and BLB nodes. The
lower NMOS transistors have their substrate terminal connected to ground or to the most
negative terminal. This substrate connection in NMOS and PMOS transistor is done so as to
reverse bias the channel.

Figure 4.1: Conventional 6T SRAM

In figure 4.2, the threshold voltage in the lower NMOS transistors of conventional 6T SRAM
has increased by applying a negative voltage source of 0.5 V. Increasing DC voltage beyond
this value lead to increase in power consumption. Threshold voltage does not depend only
upon the substrate bias but depends upon various other factors such as poly silicon metal,
37
work function of silicon dioxide (SiO 2), charge in the depletion region, gate oxide
capacitance. So application of DC source to the substrate can increase the threshold voltage
till certain extent only. The results have been shown in table 1 below. Here MN1 and MN2
represent the lower NMOS transistors.

Transistor Conventional New scheme

MN1 500 mV 595.2673 m V
MN2 478 m V 616.7711 mV

Table 1: Variation of threshold voltage

Figure 4.2: Threshold increase in 6T SRAM cell

38
 Figure 4.3: Proposed circuit in 6T SRAM cell

Figure 4.3 shows the implementation of increased threshold as well as the stacking effect.
The basic idea behind the stacking effect has already been explained in section 3. So the
upper PMOS transistors have been stacked. The transistor sizes have been reduced to half to
manage the area complexity. If the threshold voltage of both the transistors was increased, it
resulted in increased power consumption. So to avoid this problem stacking on the pull up
transistors is employed. The table showing the variation of power consumption in three variants of
6T SRAM cell is shown below.

6T Conventional Vth increased Proposed

Write 36.1833 p W 17.6211 p W 14.4279 p W

Read 36.2057 p W 17.6436 p W 14.1279 p W

Table 2: Power consumption in 6T SRAM cell

The leakage current dominates mainly during the hold state. The leakage current has interesting
property of exponentially increasing with temperature. So the leakage current is calculated for all
three circuits and at two temperatures. The result has been calculated at the room temperature
25°C and at an elevated temperature 125°C. The values have been shown in the table below.

6T Conventional Vth increased Proposed

39
 25°C 29.7678 p A 19.4389 p A 16.16488 p A
125°C 4.9262 n A 4.7268 n A 4.6918 n A

Table 3: Leakage current variation in 6T SRAM cell

When the temperature is 25°C, the leakage current is in pico amperes, but when the
temperature is increased, the leakage current is in nano amperes. Thus it can be clearly stated
that the effect of leakage current is more pronounced at higher temperatures. These analyses
have been made on 7T and 5T SRAM cells also. The circuit diagrams as well as the power
consumption are shown in the following thesis.

4.2 Simulation Results of 7T SRAM cell

Figure 4.4 shows the circuit diagram of conventional 7T SRAM cell. When compared to
conventional 6T SRAM cell, extra transistor MN5 with the control signal ‘w’ is used. The
supply voltage remains the same. An extra control signal ‘r’ to control one of the pass
transistors is also used. The 7T SRAM cell is more stable as compared to 6T SRAM cell.

Figure 4.4: Conventional 7T SRAM

40
 Figure 4.5: Threshold increase in 7T SRAM

Figure 4.4 and 4.5 shows the circuit diagram of conventional 7T SRAM and 7T SRAM with
increased threshold voltage respectively. Figure 4.6 shows the circuit diagram where both
the stacking as well as increased threshold voltage has been employed. The procedure for the
simulation and calculation of various parameters remain same as for the 6T SRAM cell.

Figure 4.6: Proposed circuit in 7T SRAM cell

41
The power consumed by the circuit in the read and write operation is shown in the table 4.
The power is in the Pico watts. The cell while performing both these operations is in the
active state. The reason of reduction in the power dissipation during active mode is that out of
7 transistors 3 to 4 transistors remain in off state. So even in the active state power is reduced
by increasing the sub threshold current.

7T Conventional Vth increased Proposed

Write 33.6156 p W 16.6420p W 9.2067 p W

Read 33.6156 p W 15.9138p W 9.4155 p W

Table 4: Power consumption in 7T SRAM cell

The leakage current at two temperatures has been calculated and the result has been shown in table
5. The results clearly show that the leakage current is greatly increased at higher temperature. At
25°C, the current is in pico amperes whereas at 125°C, the current is in nano ampere.

7T Conventional Vth increased Proposed

25°C 30.4876 p A 19.5874 p A 17.7494 p A

125°C 4.9593 n A 4.7355 n A 4.6912 n A

Table 5: Leakage current in 7T SRAM cell

4.3 Simulation results of 5T SRAM cell

Figure 4.7 shows the circuit diagram of conventional 5T SRAM cell. It can be seen that only
a single bit line and single access transistor is used. Hence the area consumed is less. Here
extra requirement of pre charge circuit is present. A pre charging voltage of 600mv is used.
‘q’ represents the storage node. ‘wl’ and ‘bl’ act as two control signals. The data is stored at
the node ‘q’ and whatever data is to be written is provided at ‘bl’. MP3, MN1and MP1, MN2
forms the pair of cross coupled inverters.

42
 Figure 4.7: Conventional 5T SRAM

All the three operations that is read, write and hold are performed and output waveforms are
obtained. Figure 4.8 shows the schematic of 5T SRAM cell, which involves the usage of DC
bias to increase the threshold voltage of lower NMOS transistors. The substrate terminal of
the lower transistors is connected to ground terminal and the substrate terminal of the upper
PMOS transistors is connected to the supply voltage of 1.8 V.

Figure4.8: Increased threshold in 5T SRAM cell

43
 Figure 4.9: Proposed 5T SRAM cell

The procedure employed for the analysis of the conventional 5T SRAM cell is similar to the
one employed for 7T and 6T memory cells. Application of DC bias does not produce an
extra penalty in the circuit as the memory arrays are mainly used in processors. And in these
processors various voltage sources are used. So supply voltage can be arranged within the
internal circuit of processer. In case of 5T SRAM cell, bit line is pre charged to a voltage of
0.6 V for the proper read and write operation.

Conventional Vth increase Proposed

5T Write 35.5898p W 17.7864p W 14.3334p W

Read 35.0267p W 17.1884p W 14.3321p W

Table 6: Power consumption in 5T SRAM cell

In table 6, pW represents the power in pico watts. Results show around 50% decline in the power
consumption, when the threshold voltage of the lower NMOS transistor is increased. If the PMOS
transistors are stacked the power too gets reduced. These results have been calculated at 25°C.
During the hold operation, WL is de asserted and the current flowing in the circuit is the total
leakage current. This current is calculated at the room temperature as well as at 125°C. The table 7
shows the variation of leakage current at two temperatures.
44
 Temperature Conventional Vth increase Proposed

5T 25°C 17.6493 p A 8.7658 p A 6.7968 p A

125°C 2.483 n A 2.28534 n A 2.230 n A

Table7: Leakage current variation in 5T SRAM cell

4.4 SNM and Read Write Waveforms

The test setup required for the calculation of Static Noise Margin has already been explained
in section 2. SNM for all the techniques has also been calculated and the graph remains
normally same. It can be shown that SNM for 7T SRAM is more as compared to that of 6T.
Figure 4.10 shows the stability curve for proposed circuit in 7T SRAM cell. Figure 4.11
shows the same scheme employed in 6T SRAM cell. The SNM curve for the 5T SRAM cell
is shown in figure 4.12.

Figure 4.10: SNM for proposed 7 T SRAM cell

45
 Figure 4.11: SNM for proposed 6T cell

Figure 4.12: SNM for proposed 5T cell

The table comparing the Static Noise Margin with the conventional circuit is shown in the table 8. It
can be clearly seen that degradation in this parameter is not too much. Moreover the optimum
value for the static noise margin generally lies within 0.3 V to 0.7 V. The values of the result lie well
within this range.

Conventional Proposed
6 T SRAM 0.59V 0.54V
7T SRAM 0.65V 0.61V
5T SRAM 0.55V 0.50V

Table 8: SNM of Conventional and Proposed Cells

For each circuit configuration, read and write waveforms have been simulated. The results
almost remain same for each configuration of cell. The result for 6T memory cell has been
shown in figure 4.13 and 4.14. The input is provided in the form of pulse. Figure 4.13 shows
the characteristics during write operation. The inputs are WL, BL, BLB and the outputs are
taken at Q and QB. It can be seen that when WL is active high, whatever data is present at the
BL same data is stored at Q.

46
Figure 4.13: Write operation in conventional 6T cell

Figure 4.14: Read operation in conventional 6T SRAM cell

47
4.5 Stacked 7T SRAM Cell

Figure 4.15 shows the schematic of a 7T SRAM cell in which the one NMOS and one PMOS
transistors are added to the lower half. Here extra control signal ‘WS’ is used during read as
well as write operation. This circuit has already been proposed for 6T SRAM cell [27]. The
‘WS’ remain low during write 0 operation and high for write 1 operation. However, here
instead of pulse input DC source is provided as the input. Table 9 shows the corresponding
results.

Operation Conventional Proposed work

Write 1 33.9085p watt 13.3408p watt
Write 0 34.1093p watt 17.9774p watt
Read 1 33.9085p watt 13.3649p watt
Read 0 34.1093p watt 18.3447p watt

Table 9: Power consumption of the proposed work

Figure 4.15: Proposed 7T SRAM cell

Read and write waveforms for the proposed work are shown below.

48
 Figure 4.16: Read 0 and Write 0 operation

In read 0 operation storage node contains logic 0 and QB contains logic 1. The output is taken
from the BL and BLB. For a correct read operation BL must provide logic0 and BLB must
provide logic1. Figure 4.16 corresponds to write 0 operation. The data to be written that is
logic 0 is provided to BL and its complement is provided to BLB.

Figure 4.17: Read 1 operation

49
 Figure 4.18: Write 1 operation

Similarly for write and read logic 1, the waveforms are shown above. Thus, these schemes
can be employed in the conventional SRAM array so as to reduce leakage current and hence
increase the battery life of the device. Moreover the system reliability too is not affected.
Each cell configuration has its own advantages. Depending upon their characteristics, they
can be employed. For example, it is advisable to used memory array comprising of 7T cells
where stability is prime concern. Secondly if the application area demands the use of
symmetrical cell 6T cell shall be preferred.

50
 CHAPTER 5

CONCLUSION

5.1 Conclusion

As microprocessors and other electronics applications get faster and faster, the need for large
quantities of data at very high speeds increases, while providing the data at such high speeds
gets more difficult to accomplish. As microprocessor speeds increase from 25 MHz to 100
MHz, to 250 MHz and beyond, systems designers have become more creative in their use of
cache memory and other high-speed methods for accessing memory. The leakage current is
continuously increasing with the scaling of devices. So for proper functioning and improve
the battery life of the devices, the techniques must be employed to reduce the power
dissipation when the device is not in use. This thesis presents certain techniques to reduce the
power dissipation in standby mode. Secondly the stability of the cell has also been checked.
The results show around 45 % power reduction when these techniques are employed. In the
proposed technique, the SNM do degrade, but it lies well within the normal range.

51
 5.2 Future Work

The techniques have been employed in 5T, 6T, 7T SRAM cells. These techniques can be
further used in SRAM cells designed using larger number of transistors. Secondly, some
other process level or circuit level may also be employed keeping the stability of the device in
mind.

52
 CHAPTER 6

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