QUESTION A B C D

The …….. Method of simplifying the boolean

1 K-map Quine Mc Clusky Algebraic VEM B
functions is also called as the tabular method

A standard SOP form has terms that have all

2 SUM SUB PRODUCT DIV A
the variables in the domain of the expression.

What logic function is produced by adding an

3 NAND NOR XOR OR A
inverter to the output of an AND gate ?

Route the data from Select data from several

Perform serial to parallel
4 A demultiplexer is used to single input to one inputs and route it to All of these A
conversion
of many outputs single output

If a logic gates has four inputs, then total

5 4 8 16 32 C
number of possible input combinations is

6 The gray code equivalent of (1011) is 1101 1010 1111 1110 D

The parity of the given binary number

7 odd even 4 8 A
100110011 is

8 In which operation carry is obtained? Addition Division Multiplication Subtraction A

 If A, B and C are the inputs of a full adder then
9 A AND B AND C A OR B AND C A OR B OR C A XOR B XOR C D
the sum is given by

One application of a digital multiplexer is to parallel-to- serial data

10 code conversion parity checking data generation C
facilitate: conversion

2 variable k-map consists of ……. Rectangular

11 4 2 8 16 A
boxes

Each product term of a group, w’.x.y’ and w.y,

12 Sum-of-Minterms Sum of Maxterms input POS A
represents the ____________in that group

The prime implicant which has at least one

Essential Prime
13 element that is not present in any other Implicant Complement Prime Complement A
Implicant
implicant is known as ___________

The …….. Is a group of minterms which

Essential Prime
14 cannot be combined with any other minterm of Prime Implicant Prime number None of these B
Implicants
groups.

For a three variable combinational circuits,

15 IIM(1,4,7) IIM(1,4) IIM(4,7) IIM(0,2,3,5,6) D
m(1,4,7) = ---------

16 Which of the following is not a multiplexer? 8-to-1 line 16-to-1 line 4-to-1 line 1-to-4 line D

In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then

17 Y0 Y1 Y2 Y3 D
the output will be ___________
 Which digital system translates coded
18 Encoder Decoder Counter Display B
characters into a more useful form?

A Karnaugh map The Karnaugh map Karnaugh maps provide a

Variable complements
Which statement below best describes a can be used to eliminates the need for visual approach to
19 can be eliminated by D
Karnaugh map? replace Boolean using NAND and NOR simplifyin g Boolean
using Karnaugh maps.
rules. gates. expression s.

20 A half-adder does not have . carry in carry out two inputs all of the above A

which are the following are examples of

21 counters registers adders PAL C
combinational circuits

22 The gray code equivalent of (1011) is 1101 1010 1111 1110 D

The parity of the given binary number

23 odd even 4 8 A
100110011 is

Each individual term in the standard SOP form

24 minterm maxterm Literal both A &B A
is called as---

25 The IC 7483 is a ---- BCD adder comparator multiplexer demultiplexer A

How many full adders are required to construct

26 m/ 2 m-1 m m+1 B
an m-bit parallel adder ?
27 Convert BCD 0001 0111 to binary. 10101 10001 10010 11000 C

If A, B and C are the inputs of a full adder then

28 A AND B AND C A OR B AND C A OR B OR C A XOR B XOR C D
the sum is given by

The decimal equivalent of the excess-3 number

29 970.42 1000 1200 970 A
110010100011.01110101 is

30 29 input circuit will have total of enteries 32 512 64 256 B

A ----group should be eliminated because it

31 increase the number number of gates requied Adjacent redundant don't care none of these B
to realize the minimized expression

Don't care condition (X) may be assumed to be

32 0 1 0 or 1 none of these C
----

In K-maps input values are ordered in ---- code

33 Binary Gray decimal none of these B
sequence

The …….. Is a group of minterms which

Essential Prime
34 cannot be combined with any other minterm of Prime Implicant Prime number None of these B
Implicants
groups.
The logical expression in standard POS form
can be represented on K-map by entering
35 1's 0's 1's and 0's Don’t' care B
…….. In the cells corresponding to each
maxterm present in the equatiion
36 This state should be avoided in SR FF 00 01 10 11 D

This is toggle condition in MS JK FF for JK

37 00 01 10 11 D
input

38 Race arround condition in JK FF is avoided in SR FF D FF MS JK FF None C

39 This is the input which is independent of clock JK SR Preset None C

Asynchronous
40 Ripple counter is also called as Synchronous counter Ring Counter Jonshon counter A
counter

41 If we short JK input , JK FF is converted into D FF T FF SR FF None B

In this counter Q is connected to J input and Asynchronous

42 Synchronous counter Ring Counter Jonshon counter C
Qbar is connected to K input counter

In this counter Q bar is connected to J input Asynchronous

43 Synchronous counter Ring Counter Jonshon counter D
and Q is connected to K input counter

44 BCD counter counts 1 to 15 1 to 9 1 to 10 None B

 In this machine output depends on input and
45 Melay machine Moore machine Both None A
state

Asynchronous
46 SISO, SIPO, PIPO,PISO are types of Shift register both None B
counter

If we design 2 bit up counter using D FF D1 D1=Q1 xor Q2 D2=Q2

47 D1=Q1Q2 D2=Q1 D1=Q1 xor Q2 D2=Q2 None B
and D2 will be bar

How many FFs are required for 4 bit up down

48 1 2 3 4 D
counter

One JK FF and one SR

49 MS JK FF is combination of Two SR FF Two JK FF None C
FF

To design Mod -4 counter using ripple counter,

50 1 2 3 4 C
how may JK FFs are required

Asynchronous
51 Excitation table is used in design of Ripple counter Synchronous counter None C
counter

52 Bushing is used to avoid Lockout condition race arround condition Both None A

J1= Q2 bar K1=Q2 bar J2=1 K2=1 (Q1is MSB

53 2 bit up counter 2 bit down counter 2 bit up down counter None B
and Q2 is LSB) , it is equation of
54 D FF is also known as Data FF Delay FF both None C

input clock pulses

Synchronous counters eliminate the delay input clock pulses are input clock pulses are input clock pulses are
are applied only to
55 problems encountered with asynchronous applied only to the last not used to activate any applied simultaneously to D
the first and last
(ripple) counters because the: stage of the counter stages each stage
stages
presetting one flip-flop clearing one flip-flop
To operate correctly, starting a ring counter clearing all the flip-
56 and clearing all the and presetting all the presetting all the flip-flops B
requires: flops
others others

In sequential circuit output states depends Present input as well as

57 Past input states Present input state None C
upon past output

On a master-slave flip-flop, when is the master when the gate is

58 when the gate is HIGH both of the above neither of the above A
enabled? LOW

Which table shows the logical state of a digital

59 circuit output for every possible combination Function table Truth table Routing table ASCII table B
of logical states in the inputs ?

A J-K flip-flop is in a "no change" condition

60 J = 1, K = 1 J = 1, K = 0 J = 0, K = 1 J = 0, K = 0 D
when ________.

In Sequential circuit the output state depend Present as well as Past

61 Past input State Present input State None of Above C
upon input

62 How is a J-K flip-flop made to toggle? J=0 , K= 0 J=0 , K=1 J=1 , K=0 J=1 , K=1 D
 A J-K flip-flop is in a "no change" condition
63 J=0 , K= 0 J=0 , K=1 J=1 , K=0 J=1 , K=1 A
when ________.

Sequetial circuit used for counting pulses is

64 Counter Register Flip flop None A
known as -----

If T flip flop function is obtained from a JK

65 J=K=1 J=K=0 J =1, K = 0 None of the above A
flip flop, if ........

66 when a flip flop is set ,its output will be --------- 0 1 cants say NONE B

What is a shift register that will accept a

67 parallel input, or a bidirectional serial load and tristate end around universal Conversion C
internal shift features, called?

To operate correctly, starting a ring shift clearing all the flip- presetting one flip-flop clearing one flip-flop
68 presetting all the flip-flops B
counter requires: flops and clearing all others and presetting all others

A serial in/parallel out, 4-bit shift register

initially contains all 1s. The data nibble 0111 is
69 0 1111 O111 1000 C
waiting to enter. After four clock pulses, the
register contains ________.
If a logic circuit does not contain any feedback
Combinational logic
70 loops, and the output is wholly dependent on Sequential logic circuit Delay logic circuit Adder A
circuit
the input, it is called a
Determine the output frequency for a
frequency division circuit that contains 12 flip-
71 10.24 kHz 5 kHz 30.24 kHz 15 kHz B
flops with an input clock frequency of 20.48
MHz.
 The logic level at The Q output is The Q output is
Which statement BEST describes the operation the D input is ALWAYS identical to ALWAYS identical to The Q output is ALWAYS
72 A
of a negative-edge-triggered D flip-flop? transferred to Q on the CLK input if the D the D input when CLK = identical to the D input.
NGT of CLK. input is HIGH. PGT.

How many flip-flops are required to produce a

73 1 4 6 7 D
divide-by-128 device?

An invalid condition in the operation of an HIGHs are applied LOWs are applied a LOW is applied to the a HIGH is applied to the S
74 active-HIGH input S-R latch occurs when simultaneously to simultaneously to both S input while a HIGH is input while a LOW is A
________ both inputs S and R inputs S and R applied to the R input applied to the R input
On the fifth clock pulse, a 4-bit Johnson
sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = Q0 = 1, Q1 = 0, Q2 Q0 = 1, Q1 = 1, Q2 = 1, Q0 = 0, Q1 = 0, Q2 = 1, Q0 = 0, Q1 = 0, Q2 = 0,
75 C
1. On the sixth clock pulse, the sequence is = 0, Q3 = 0 Q3 = 0 Q3 = 1 Q3 = 1
________.
It is a bi-directional counter capable of
Up Synchronous Down Synchronous
76 counting in either of the direction depending Synchronous Counter Both A and B D
Counter Counter
on the control signal

The terminal count of a modulus-11 binary

77 1010 1000 1001 1100 A
counter is ________.

Synchronous construction reduces the delay all flip-flops and all flip-flops and gates
78 a single gate a single flip-flop and a gate D
time of a counter to the delay of: gates after a 3 count
The counter can The count sequence cannot
The counter can be In general, the counter
Which of the following statements best count in either be reversed, once it has
reversed, but must be can be reversed at any
79 describes the operation of a synchronous up- direction, but must begun, without first C
reset before counting in point in its counting
/down-counter? continue in that resetting the counter to
the other direction. sequence.
direction once zero.
The parallel outputs of a counter circuit
80 parallel data word clock frequency counter modulus clock count D
represent the:
 First programmable Field Programmable First Program Gate
81 The FPGA refers to ____________ Field Program Gate Array B
Gate Array Gate Array Array

Very Long Single Very Least Scale Very Large Scale Very Long Scale
82 The full form of VLSI is ____________ C
Integration Integration Integration Integration

In FPGA, vertical and horizontal directions are

83 A line A channel A strobe A flip-flop B
separated by ____________

84 Applications of PLAs are _____________ Registered PALs Configurable PALs PAL programming All of the Mentioned D

The inputs in the PLD is given through

85 NAND gates OR gates NOR gates AND gates D
____________

To protect from To implement the

86 Why antifuses are implemented in PLD? To increase the memory As a switching devices C
high voltage programmes

State Box, Decision State Box, Decision Box, Input Box, Output Box,
87 What are the basic elements in ASM chart? None of these D
Box, Output box Input Box State Box

Every FSM state Every FSM transition

While converting a FSM state diagram to an Every FSM state will
88 will map into an will map into a Decision None of these. A
ASM chart, which of the following is true map into a State Box.
ASM Block. Box.
4 elements i.e. input, 5 elements i.e. clock
2 elements i.e. state 3 elements i.e. state box,
state box, conditional pulses, input, state box,
89 ASM chart is composed of box and decision conditional output box, B
output box, and decision conditional output box and
box and decision box
box decision box
 programmable load Programmable logic Programmable loaded
90 The full form of PLD is programmable logic data C
devices devices devices

thousands of basic logic

The content of a simple programmable logic thousands of basic gates and advanced advanced sequential logic
91 fuse-link arrays C
device (PLD) consists of: logic gates sequential logic functions
functions

How many combinations are handled in a

92 4 16 8 32 B
LUT?

Transistor–transistor logic (TTL) is a class of Bipolar junction Bipolar junction transistors

93 JFET only Resistors D
digital circuits built from ____________ transistors (BJT) (BJT) and resistors

TTL is called transistor–transistor logic

because both the logic gating function and the Bipolar junction Resistors and transistors
94 Resistors One transistor B
amplifying function are performed by transistors respectively
____________

95 TTL was invented in 1961 by ____________ Baker clamp James L. Buie Chris Brown Frank Wanlass B

Transistor-
Transistor-coupled Transistor-capacitor Transistor-complementary
96 The full form of TCTL is ____________ complemented transistor A
transistor logic transistor logic transistor logic
logic

Transistor-transistor Multiple-emitter
97 TTL inputs are the emitters of a ____________ Resistor-transistor logic Diode-transistor logic B
logic transistor

98 TTL is a ____________ Current sinking Current sourcing Voltage sinking Voltage sourcing A
 Standard TTL circuits operate with a __ volt
99 2 4 5 3 C
power supply.

TTL devices consume substantially ______

100 Less More Equal Very High B
power than equivalent CMOS devices at rest.

Which of the following is the fastest logic

101 CMOS TTL DTL ECL D
family

102 TTL is a ____________ Current sinking Current sourcing Voltage sinking Voltage sourcing A

The digital logic family which has the lowest

103 CMOS TTL ECL PMOS C
propagation delay time is

Diodes and Bipolar Bipolar transistors and

104 Digital circuits mostly use Diodes Bipolar transistors C
transistors FETs

Which of the following is not the advantage of Low power

105 High switching speeds Small size Good immunity to noise B
MOS gates? dissipation

In a positive logic system, logic state 1

106 Positive voltage Zero voltage level Lower voltage level Higher voltage level D
corresponds to

The main disadvantage of TTL with totem pole High power Wire ANDing operation
107 Low fan out Low noise margin B
output is dissipation is not allowed
 Which TTL logic gate is used for wired
108 Totem Pole Tri state output Open collector output ECL gates C
ANDing

109 Microprocessor consists of? ALU register array control unit All of the above D

The __________ controls the flow of data and

110 control unit register array accumulator ALU A
instructions within the computer.

Which Unit Provodes timing signal for

Timing and control
111 synchronization of events and provides control Timing Unit control Unit Instruction unit A
Unit
signal?

Which Unit of Microprocessor is used to

112 ALU Accumlator control Unit Instruction unit A
perform Arithmatic and logical operations

113 IC 74181 is a ------------ Multiplexer IC Demultiplxer IC ALU IC Adder IC C

In Ic 74181 ,Mode control input M=0 is used Arithmetic Arithmatic and Logic
114 logic operation All of the mentioned A
for --------------- operation operations

Memory Hierarchy of microprocessor explains

115 that the nearaer the memoey to the processor --- Fast slow Medium avrage A
---------------- is its access

Static Ram ( SRAM ) is made up of --------------

116 Capacitors Flip Flop MOSFET BJT B
--
 Dynamic Ram ( DRAM ) is made up -------------
117 Flip Flop MOSFET BJT Capacitors D
------------

Continuous refreshing is required in --------------

118 SRAM DRAM ROM EPROM B
---------

119 Address bus is ----------------------- Unidirectional Bidirectional Unipolar None of the above A

In Ic 74181 ,Mode control input M=1 is used Arithmetic Arithmatic and Logic
120 logic operation All of the mentioned B
for --------------- operation operations

121 Ic 74181 is a ------------ Pin IC 12 Pin 24 Pin 14 Pin None of the mentioned B

The Register which is used to store temporary

122 Accumulator Reg.B Stack Pointer Program Counter A
data is ?