AMBA

AHB (Advanced High-Performance Bus)

The AHB protocol is part of the AMBA 2 standard, introduced to provide a high-performance,
system-level bus for communication between different components of a SoC (System-on-Chip).

Features of AHB

1. Single-Clock Edge Operation:

o AHB operates on a single clock edge for simplicity and better performance.

2. High Bandwidth:

o Designed to support high data throughput with pipelined operations.

3. Burst Transfers:

o Supports multiple data transfers (burst) with a single address phase.

4. Single Master Access:

o At any time, only one master has access to the bus, simplifying arbitration.

5. Pipelined Address and Data Phases:

o Increases bus efficiency by overlapping the address and data phases of successive
transfers.

6. Split and Retry Support:

o The slave can deassert its response (e.g., when busy), allowing retries.

7. Wide Data Bus Support:

o Supports 8, 16, 32, and 64-bit data buses.

AHB Bus Components

1. Master: Initiates read/write operations and controls the address and data phases.

2. Slave: Responds to the master's requests.

3. Arbiter: Determines which master can access the bus when multiple masters are requesting.

4. Decoder: Decodes the address from the master and routes the request to the appropriate
slave.

AHB Transfer Types

1. Single Transfer: Transfers a single word of data.

2. Incrementing Burst: Transfers multiple data words to sequential addresses.

 3. Wrapping Burst: The address wraps around a boundary, useful for cache line accesses.

AHB Operation Phases

1. Address Phase:

o The master drives the address and control signals.

2. Data Phase:

o Data is transferred between the master and slave.

3. Response Phase:

o The slave provides a response: OKAY, ERROR, SPLIT, or RETRY.

AHB-Lite

 A simplified version of AHB introduced in AMBA 3.

 Designed for single-master systems to reduce complexity and cost.

 Removes split and retry capabilities.

ASB (Advanced System Bus)

The ASB protocol is part of the AMBA 1 specification, introduced in the late 1990s. It was designed
as a high-performance bus for communication between components in a System-on-Chip (SoC).
Although ASB has been largely replaced by AHB and AXI in modern designs, it was a significant step
forward in enabling synchronous, efficient data transfers.

Features of ASB

1. Single-Clock Edge Operation:

o All operations occur on the rising edge of the system clock.

2. Multiple Masters:

o ASB supports multi-master systems, allowing multiple masters to initiate

transactions.

3. Burst Transfers:

o ASB supports burst transfers for improving data throughput.

4. Address and Data Phases:

o A single address phase followed by one or more data phases.

 5. Synchronous Bus Protocol:

o Both address and data transfers occur in a synchronous manner, improving bus
performance.

6. Wait State Insertion:

o The slave can introduce wait states if it is not ready to respond, enabling slower
peripherals to interface.

ASB Bus Components

1. Master: Initiates read or write transactions.

2. Slave: Responds to the master’s requests.

3. Arbiter: Controls which master gains access to the bus in multi-master systems.

4. Decoder: Decodes the address from the master and selects the appropriate slave.

ASB Operation

1. Address Phase:

o The master places the address and control signals on the bus.

2. Data Phase:

o Data is transferred between the master and slave.

o Burst transfers allow multiple data words to be sent after a single address phase.

3. Wait States:

o If the slave cannot respond immediately, it can introduce wait states to delay the
transfer.

ASB Limitations

1. No Pipelining:

o ASB does not support pipelining, limiting its efficiency compared to AHB and AXI.

2. Basic Burst Support:

o Burst transfers are supported but are less flexible than those in AHB and AXI.

3. Lacks Advanced Features:

o Does not support split transactions, out-of-order execution, or independent

read/write channels like AXI.
APB (Advanced Peripheral Bus)

The APB protocol is part of the AMBA (Advanced Microcontroller Bus Architecture) standard. It is
designed for low-bandwidth, low-power, and simple peripheral communication in a System-on-
Chip (SoC). APB is commonly used to connect peripherals such as timers, UARTs, and GPIOs to the
main bus system.

Key Features of APB

1. Low Complexity:

o APB is designed for simplicity, with minimal control signals and no pipelining.

2. Single-Clock Operation:

o All transfers occur on the rising edge of a single clock signal, reducing complexity.

3. Low Power Consumption:

o APB's simplicity and lack of high-speed operation make it ideal for power-sensitive
applications.

4. No Burst Support:

o APB supports single data transfers only—it does not allow bursts.

5. Address and Data Phase Separation:

o Each APB transfer consists of two distinct phases: an address phase followed by a
data phase.

6. Read and Write Transfers:

o Supports simple read and write operations between the master and slave.

APB Bus Components

1. Master:

o Controls the bus and initiates read/write transfers.

2. Slave:

o Responds to the master's requests, such as peripherals (GPIO, UART, etc.).

3. Bridge:

o Connects APB to higher-performance buses like AHB or AXI.

APB Operation

Each APB transfer has two phases:

 1. Address Phase:

o The master drives the address and control signals onto the bus.

o The address specifies the peripheral (slave) to be accessed.

2. Data Phase:

o The master transfers data for a write operation or receives data from the slave for a
read operation.

The transfer is complete when PENABLE is asserted by the master and the slave responds with valid
data.

AXI

AXI (Advanced eXtensible Interface)

The AXI protocol is part of the AMBA 3 and AMBA 4 standards. It is a high-performance, high-
bandwidth bus interface used in modern System-on-Chip (SoC) designs. AXI provides advanced
features like independent read and write channels, outstanding transactions, and burst transfers,
making it ideal for high-speed communication between masters and slaves.

Key Features of AXI

1. Independent Read and Write Channels:

o AXI separates read and write data channels for parallel operation, increasing
efficiency.

2. Multiple Outstanding Transactions:

o Supports multiple in-progress transactions with unique IDs to distinguish them.

3. Burst Transfers:

o AXI allows bursts where only the starting address is sent.

o Types of bursts: Fixed, Incrementing, and Wrapping.

4. Unaligned Data Transfers:

o Supports unaligned address/data transfers for flexibility.

5. Out-of-Order Completion:

o Transactions can complete out of order using IDs to maintain sequence.

6. Low Latency and High Throughput:

o Designed for high bandwidth and low latency with minimal arbitration delays.

7. Support for QoS (Quality of Service):

o Provides AWQOS and ARQOS signals for priority-based transactions.

AXI Signals

1. Write Transaction

 Write Address Channel:

o Signals: AWADDR (Address), AWVALID, AWREADY.

  Write Data Channel:

o Signals: WDATA (Data), WSTRB (Byte Enable), WVALID, WREADY.

 Write Response Channel:

o Signals: BRESP (Response), BVALID, BREADY.

2. Read Transaction

 Read Address Channel:

o Signals: ARADDR (Address), ARVALID, ARREADY.

 Read Data Channel:

o Signals: RDATA (Data), RRESP (Response), RVALID, RREADY.

AXI Burst Transfers

 AXI supports three types of bursts:

1. Fixed Burst: Address remains the same for each transfer.

o Example: Accessing a peripheral register.

2. Incrementing Burst: Address increases with each transfer.

o Example: Accessing sequential memory locations.

3. Wrapping Burst: Address wraps around after a specific boundary.

o Example: Accessing a cache line.

Advantages of AXI

1. High Performance:

o Independent read/write channels and burst transfers improve bandwidth.

2. Scalability:

o Supports multiple masters and slaves.

3. Flexibility:

o Handles unaligned data transfers, out-of-order completion, and QoS.

4. Low Latency:

o Parallel operation of channels reduces transaction delays.

COMPARISON B/W AHB, ASB, APB, AXI