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Combinational Circuit Design

This document summarizes key concepts in combinational circuit design including: 1) Bubble pushing, compound gates, logical effort, and input ordering techniques for optimizing gate-level designs. 2) The use of asymmetric, skewed, and asymmetric skewed gates to optimize timing by favoring critical inputs and transitions. 3) How to select transistor widths in gates to achieve balanced rise/fall times or minimize average delay, including that the best P/N ratio is the square root of the equal delay ratio.

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Rajdeep Dash
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
100 views

Combinational Circuit Design

This document summarizes key concepts in combinational circuit design including: 1) Bubble pushing, compound gates, logical effort, and input ordering techniques for optimizing gate-level designs. 2) The use of asymmetric, skewed, and asymmetric skewed gates to optimize timing by favoring critical inputs and transitions. 3) How to select transistor widths in gates to achieve balanced rise/fall times or minimize average delay, including that the best P/N ratio is the square root of the equal delay ratio.

Uploaded by

Rajdeep Dash
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture 9:

Combinational Circuit Design

Outline
Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Example 1
module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates.


D0 S Y D1 S
10: Combinational Circuits CMOS VLSI Design 4th Ed. 3

Example 2
2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

D0 S Y D1 S

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Bubble Pushing
Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgans Law
Y (a) (b) Y

Y (c) D (d)

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Example 3
3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.

D0 S D1 S

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Compound Gates
Logical Effort of compound gates
Y=A
Y = Ai B + C

Y = Ai B + C i D

Y = Ai( B + C ) + D i E

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Example 4
The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the two designs. H = 160 / 16 = 10 B = 1 N = 2
D0 S Y D1 S
P =2+2 =4 G = (4 / 3)i(4 / 3) = 16 / 9 F = GBH = 160 / 9 f = N F = 4.2 D = Nf + P = 12.4
10: Combinational Circuits

D0 S D1 S
P = 4 +1 = 5 G = (6 / 3)i(1) = 2 F = GBH = 20 f = N F = 4.5 D = Nf + P = 14

CMOS VLSI Design 4th Ed.

Example 5
Annotate your designs with transistor sizes that achieve this delay.
8 8 8 8 8 8 8 8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

10 25 25 25 25 Y 10 6 6

10 10 6 6 24 12 Y

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

Input Order
Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2 If B arrives latest? 2.33
2 2 2x 6C 2C

2 A B

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

10

Inner & Outer Inputs


Inner input is closest to output (A) Outer input is closest to rail (B) If input arrival time is known Connect latest input to inner terminal

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

11

Asymmetric Gates
Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) A Boost size of noncritical input reset So total resistance is same gA = 10/9 2 2 Y A 4/3 gB = 2 4 reset gtotal = gA + gB = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up
10: Combinational Circuits CMOS VLSI Design 4th Ed.

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Symmetric Gates
Inputs can be made perfectly symmetric

2 A B 1 1

2 1 1

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

13

Skewed Gates
Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nMOS transistor
HI-skew inverter 2 A 1/2 Y A 1 unskewed inverter (equal rise resistance) 2 Y A 1/2 unskewed inverter (equal fall resistance) 1 Y

Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. gu = 2.5 / 3 = 5/6 gd = 2.5 / 1.5 = 5/3
10: Combinational Circuits CMOS VLSI Design 4th Ed. 14

HI- and LO-Skew


Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction But larger for the other direction
10: Combinational Circuits CMOS VLSI Design 4th Ed. 15

Catalog of Skewed Gates


Inverter NAND2
2 2 Y Y gu = 1 u gd = 1 d gavg = 1 avg A B 2
2

NOR2
B A gu = 4/3 u gd = 4/3 d gavg = 4/3 avg B Y A gu = 1 u gd = 2 d gavg = 3/2 avg B Y A gu = 2 u gd = 1 d gavg = 3/2 avg 1 1/2
1

4 4 Y
1

unskewed

2 A
1

gu = 5/3 u gd = 5/3 d gavg = 5/3 avg

2 1 1

4 4 Y 1/2 gu = 3/2 u gd = 3 d gavg = 9/4 avg

HI-skew

2 A Y 1/2 gu = 5/6 u gd = 5/3 d gavg = 5/4 avg 1 A 1 Y gu = 4/3 u gd = 2/3 d gavg = 1 avg

A
B

1 2 2

2 2 Y 1 gu = 2 u gd = 1 d gavg = 3/2 avg

LO-skew

A B

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

16

Asymmetric Skew
Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input
A reset

1 A reset

2 4/3 4

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

17

Best P/N Ratio


We have selected P/N ratio for unit rise and fall resistance ( = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter P Delay driving identical inverter A 1 tpdf = (P+1) tpdr = (P+1)(/P) tpd = (P+1)(1+/P)/2 = (P + 1 + + /P)/2 dtpd / dP = (1- /P2)/2 = 0 Least delay for P =
10: Combinational Circuits CMOS VLSI Design 4th Ed. 18

P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters But significantly decreases area and power

Inverter

NAND2
2 2 Y A B 2 2 gu = 4/3 gd = 4/3 gavg = 4/3 B A

NOR2
2 2 Y 1 1 gu = 2 gd = 1 gavg = 3/2

fastest P/N ratio

1.414 Y 1 gu = 1.15 gd = 0.81 gavg = 0.98

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

19

Observations
For speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages

10: Combinational Circuits

CMOS VLSI Design 4th Ed.

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