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Assignment Questions

Uploaded by

aschkoul
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ASSIGNMENT QUESTIONS

COURSE: ADVANCED COMPUTER ARCHITECTURE CODE: TCS 704

1. What is the concept of Computer Architecture? Explain the current Technology Trends related to
Computer Architecture through cost and power consumption.
2. ISA?
3. What is Amdahl’s Law?
4. What is Moore’s Law?
5. What is Flynn’s Architecture?
6. Define Pipelining concept.
7. What is Von Neumann Architecture? How is it different from the Harvard Architecture?
8. What is the need of Parallelism and Parallel Architectures?
9. What are the various factors affecting CPU Performance?
10. 60% of a program execution time occurs inside a loop that can be executed in parallel and rest 40% in
serial. What is the maximum speedup we should expect from a parallel version of the program executing
on 6CPUs? With reference to Amdahl’s Law, solve the above question.
11. What is Lhadma’s Law?
12. Design Memory Hierarchy.
13. What is Cache Memory? What is Hit and Miss Ratio?
14. Give the performance metrics of Cache Memory.
15. Different Page Replacement Techniques used in Memory system?
16. What is Coherence?
17. Difference between Spatial and Temporal Locality?
18. What is the concept of Direct Mapping (with respect to Cache)?
19. What are the various techniques for Fast Address Translation?
20. Explain Virtual Memory in detail.
21. Explain the concept of Pipelining in detail.
22. What are the different pipeline hazards?
23. Define RISC.
24. Define CISC.
25. Explain the pipeline issues that needs to be addressed.
26. Explain the Instruction level parallelism.
27. Define the taxonomy of parallel architecture.
28. Explain in detail Instruction level parallelism.
29. A processor has a cache with a hit rate of 80%. The time to access data from the cache is 15ns, and the
time to access data from the main memory (on a miss) is 100 ns. What is the average memory access
time?
30. Differentiate between centralized and distributed shared-memory.
31. Explain the concept of message passing over shared memory.
32. Advantages of Paging and segmentation.
33. History of RISC and CISC.
34. Difference between DLP and ILP.
35. Explain the components of modern computer architecture and their interaction with each other.
36. What are the various challenges associated when implementing pipeline in a CPU?
37. Explain Pipeline Hazards.
38. Explain page table.
39. What is virtual address?
40. Explain Effective access time, if: A system uses a two-level cache (L1 and L2):
• L1 cache hit time = 10 cycle
• L1 miss rate = 10%
• L2 cache hit time = 20 cycles
• L2 miss rate = 5% and Main memory access time = 50 cycles
41. What are the various performance issues in pipelining?
42. What is Branch Prediction and Direction Predictor?
43. Explain RAW and WAW.
44. Explain the taxonomy of parallel architecture.
45. Differentiate between Centralized and Distributed shared-memory architecture.
46. Explain Message Passing vs Shared Memory?
47. What is FAT (Fast Address Translation)?

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