Salaam Faculty of

University Engineering and IT

Department of
Information Technology

Microprocessor Course for

Computer Science & Information
Technology Students
By

Dr. Saber M. E. Fadul (PhD)

Senior Member of IEEE (USA)
Member IET (UK)
BIU and EU
in 8086
Microprocessors
Block Diagram of 8086 Microprocessor  Numbers

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Block Diagram of 8086 Microprocessor  CISC and RISC
CISC Instructions
•CISC Architectures: Typically have a large instruction set, often containing hundreds to
thousands of instructions. For example:
• The x86 architecture, which includes the 8086 microprocessor, has over 1,000
instructions, including various addressing modes, complex operations, and different
data types.

RISC Instructions
•RISC Architectures: Feature a smaller instruction set, usually containing around 30 to
100 simple instructions. For example:
• ARM and MIPS architectures are well-known RISC examples, typically having about
30-100 core instructions focused on simple operations such as load, store,
arithmetic, and branch instructions.

CISC: Hundreds to thousands of instructions (e.g., x86: over 1,000)

RISC: 30 to 100 instructions (e.g., ARM, MIPS)

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Block Diagram of 8086 Microprocessor  Main Blocks/Units
In the 8086 microprocessors,3 the process of instruction execution involves four
primary stages: Fetch, Decode, Execute, and Write-back.
The microprocessor is divided into two main functional blocks:
1. the Bus Interface Unit (BIU) and
2. the Execution Unit (EU).
Both units collaborate to carry out these stages. So:
# How does each phase/unit/block work?
# What are registers included in the BIU and EU?
# How these registers perform the four primary stages to execute
instructions?
# How do we calculate the physical address for the memory?

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Block Diagram of 8086 Microprocessor  General Overview

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Block Diagram of 8086 Microprocessor

Bus Interface Unit (BIU)

https://roboticelectronics.in/architecture-of-8086/

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Block Diagram of 8086 Microprocessor

Execution Unit (EU)

https://roboticelectronics.in/architecture-of-8086/

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Block Diagram of 8086 Microprocessor  Memory Segments

Physical Address

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8086 Microprocessor  8086 microprocessor, physical addresses
In the 8086 microprocessor, physical addresses are calculated by combining a
segment address with an offset.
Step 1: Understand Segment and Offset
The 8086 uses segmentation, where memory is divided into segments. Each
segment can start at any location that’s a multiple of 16 bytes (or 10h in
hexadecimal).
The two key components for calculating a physical address are:
Segment address: 16-bit address that specifies the start of a 64 KB
segment.
Offset address: 16-bit address that specifies a location within the
segment.

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8086 Microprocessor  8086 microprocessor, physical addresses
Step 2: Formula for Physical Address

The physical address is calculated as follows:

Physical Address = (Segment×16) + Offset

This can also be represented as:

Physical Address = (Segment×10ℎ) + Offset

1. Multiply the segment address by 10h (or 16 in decimal).

2. Add the offset to this result.
3. The sum is your physical address.

This method allows the 8086 microprocessor to access a 1 MB address space, even
though it uses 16-bit registers.

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8086 Microprocessor  8086 microprocessor, physical addresses
Step 3: Calculation Example

Suppose you have:

 Segment = 1234h
 Offset = 5678h
Step-by-Step Calculation:
1. Convert the segment address to its base address by multiplying by 16:
Segment Base = 1234ℎ×10ℎ = 12340ℎ
2. Add the offset to the segment base to get the physical address:
Physical Address = 12340ℎ+5678ℎ =179B8h
Thus, the physical address is 179B8h.

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Block Diagram of 8086 Microprocessor  Operations
1. Fetch Stage (Instruction Fetch)
The Bus Interface Unit (BIU) is responsible for fetching instructions from memory.
• BIU's Role:
o The Instruction Pointer (IP) register, which stores the address of the next
instruction to be fetched, sends the memory address to the BIU.
o The BIU calculates the physical address by adding the Code Segment (CS)
register to the value of the IP (i.e., Physical Address = CS × 10H + IP).
o The instruction is fetched from memory, and the IP is incremented to point to the
next instruction.
o The fetched instruction is stored in the Instruction Queue, a 6-byte prefetch queue
inside the BIU. This allows the EU to process instructions while the BIU fetches
new ones.
• Registers involved:
o CS (Code Segment)
o IP (Instruction Pointer)
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Block Diagram of 8086 Microprocessor  Operations
2. Decode Stage (Instruction Decode)
Once an instruction is fetched, it needs to be decoded before execution.
• EU's Role:
o The EU takes the instruction from the Instruction Queue in the BIU.
o The EU decodes the opcode (operation code) to determine the type of operation to
be performed (e.g., addition, subtraction, data movement, etc.).
o If the instruction involves memory, the effective address is calculated using segment
and offset registers (e.g., DS for data or SS for stack).
• Registers involved:
o General-purpose registers: AX, BX, CX, DX (depending on the instruction)
o Segment registers: DS (Data Segment), SS (Stack Segment) for data/stack
access
o Pointer registers: BP (Base Pointer), SP (Stack Pointer) for stack addressing
o Index registers: SI (Source Index), DI (Destination Index) for string operations

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Block Diagram of 8086 Microprocessor  Operations
3. Execute Stage (Instruction Execution)
After decoding, the instruction is executed based on the operation specified.
• EU's Role:
o The ALU (Arithmetic Logic Unit) within the EU performs the operation, which may
involve arithmetic (addition, subtraction), logic (AND, OR), or data movement.
o For arithmetic instructions, the AX register (Accumulator) is often involved. For example,
if the instruction is ADD AX, BX, the EU will add the content of the BX register to the AX
register.
o Depending on the instruction, the Flag Register (Status Register) may be updated to
reflect the result of the operation, such as Zero (ZF), Carry (CF), or Sign (SF) flags.
• Registers involved:
o AX (Accumulator): Commonly used for arithmetic and data transfer
o BX, CX, DX: General-purpose registers for different instructions
o Flag Register: For status flags (e.g., Zero Flag, Carry Flag, Sign Flag)
o Segment registers (if memory is involved)
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Block Diagram of 8086 Microprocessor  Operations

4. Write-back Stage (Result Write-back)

After the execution, the result is written back to the appropriate destination.
• EU's Role:
o The result of the execution is stored either in a general-purpose register (e.g., AX, BX,
CX, DX) or in memory.
o If the instruction is MOV [BX], AX, the result in the AX register is written to the memory
address pointed to by the BX register, using the Data Segment (DS) as the base.
• Registers involved:
o AX, BX, CX, DX: General-purpose registers for holding results
o SI, DI: For indexed addressing modes (used in string operations)
o Segment registers: DS (Data Segment), SS (Stack Segment), depending on the
type of memory access

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Block Diagram of 8086 Microprocessor  Operations
Example: Instruction Cycle
Let’s walk through an example with the instruction ADD AX, BX:
1. Fetch:
o The IP sends the address of the ADD AX, BX instruction to the BIU, which fetches the instruction
from memory.
o The BIU stores the instruction in the Instruction Queue and updates the IP to point to the next
instruction.
2. Decode:
o The EU retrieves the instruction from the queue and decodes the operation. It identifies that this is
an addition operation where the BX register's contents are to be added to the AX register.
3. Execute:
o The ALU in the EU performs the addition: AX = AX + BX.
o The result of the addition is stored in the AX register.
o The Flag Register is updated based on the result (e.g., the Zero Flag is set if the result is zero).
4. Write-back:
o The result of the operation is already in the AX register, so no further memory access is needed.

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Block Diagram of 8086 Microprocessor

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