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4 views

program mem

Uploaded by

ticebekhulu.nt
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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There are two memory blocks in the PIC16F818.

These are:
1.Program memory
2.Data memory.
Each block has its own bus, so that access to
each block can occur during the same oscillator
cycle.
The data memory can further be broken down
into:
1.General purpose RAM or Registers (GPR)
2.Special Function Registers (SFRs)
The PIC16F818/819 devices have a 13-bit
program counter capable of addressing an 8K x
14 program memory space.
For the PIC16F818, the first 1K x 14 (0000h-
03FFh) is physically implemented.
For the PIC16F819, the first 2K x 14 is located at
0000h-07FFh. Accessing a location above the
physically implemented address will cause a
wraparound. For example, the same instruction
will be accessed at locations 020h, 420h, 820h,
C20h, 1020h, 1420h, 1820h and 1C20h.
The Reset vector is at 0000h and the interrupt
vector is at 0004h.
The data memory is partitioned into multiple banks that
contain:
The General Purpose Registers
The Special Function Registers.
Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank
select bits.
Each bank extends up to 7Fh (128 bytes).
The lower locations of each bank are reserved for the
Special Function Registers.
Above the Special Function Registers are the General
Purpose Registers, implemented as static RAM.
All implemented banks contain SFRs.

in another bank for code reduction and quicker access


(e.g., the Status register is in Banks 0-3).
PIC16F819 REGISTER FILE MAP
Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits.
The data memory area also contains the
data EEPROM memory.
This memory is not directly mapped into
the data memory, but is indirectly mapped.
That is, an indirect address pointer
specifies the address of the data
EEPROM memory to read/write.
The Special Function Registers are used
by the CPU and Peripheral functions to
control the device operation.
These registers are static RAM.
The special function registers can be
classified into two sets,
1.Core
2.Peripheral.
GENERAL PURPOSE REGISTER FILE

Each General Purpose Register (GPR) is 8-bits


wide

The register file can be accessed either:


1. Directly
2. Indirectly through the File Select Register, FSR.
The STATUS register contains the
arithmetic status of the ALU, the RESET
status and the bank select bit for data
memory.
As with any register, the STATUS register
can be the destination for any instruction.
If the STATUS register is the destination for an instruction that
affects the Z, DC or C bits, then the write to these three bits is
disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper three bits
and set the Z bit. This leaves the STATUS register as 000u
u1uu (where u = unchanged).
Only the BCF, BSF, SWAPF and MOVWF instructions should
be used to alter the STATUS register, because these
instructions do not affect any status bit.
1: The C and DC bits operate as a borrow and digit
borrow out bit, respectively, in subtraction. See the
SUBLW and SUBWF instructions for examples.
2: When the STATUS register is the destination for an
instruction that affects the Z, DC or C bits, then the write
to these three bits is disabled. The specified bit(s) will be
updated according to device logic
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0

IRP: Register Bank Select (used for Indirect addressing)


0 = Bank 0, 1 1 = Bank 2, 3
RP1:RP0: Register Bank Select Bits (used for direct addressing)
00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3
TO: Time-out bit
0 = A WDT time-out occurred
PD: Power-down bit
0 = SLEEP instruction executed
Z: Zero bit
1 = Result of arithmetic operation is zero
DC: Digit carry / borrow bit
1 = Carry out of 4th low order bit occurred / No borrow occurred
C: Carry / borrow bit
1 = Carry out of MSB occurred / No borrow occurred
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
(ADDRESS 81h, 181h)
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
(ADDRESS 0Dh)
SPECIAL FUNCTION REGISTER SUMMARY

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