Computer Architecture

Syllabus
❖ Objectives:
Syllabus:
❖ Understand the various types of numbers
Number Systems: Number
representations.
representations and operations on
signed numbers, Multiplication and ❖ Perform addition and subtraction operations on
division Operations. signed numbers.
❖ Design the equivalent circuits for adders.
❖ Multiplication using Booth Algorithm
❖ Division using Restoring and Non Restoring
Methods
 Numbers Representation
❖ The Major three representations used for representing the Positive and Negative Numbers are;
❖ Sign and magnitude
❖ 1’s - complement
❖ 2’s - complement
❖ In all these representation the leftmost bit (MSB) is 0 for Positive number and 1 for Negative number.
❖ In Sign and Magnitude the negative number is represented by changing the MSB bit to 1.
❖ In 1’s Complement representation the negative number is represented by complimenting the each bit
of the corresponding positive number.
❖ In 2’s-Complement representation the negative number is represented by adding 1 to the 1’s-
Complement of that number.
 Sign and Magnitude
❖ High order SIGN bit is
❖ 0 = positive (or zero), 1 = negative
❖ Remaining bit is the magnitude:
❖ Number range for n bits = (+/- ) 2n-1 -1
❖ Two representations for 0
 Complement Representation
❖ 1’s Complement
❖ Complement/inverse all the bits
❖ Still two representations of 0.
❖ 2’s Complement
❖ Only one representation of 0.
❖ Range of numbers -2n-1 to + 2n-1 -1
 Numbers Representation
❖ Consider a 4-bit machine word is
used to represent the numbers.
❖ Possible values are16 different
values which can be represented as
roughly half are positive, half are
negative.
 Addition and Subtraction
❖ The 2’s Complement system is the most ef cient method for performing the addition and
subtraction.
❖ Addition:
❖ To add two numbers, add their n-bit representation and ignore the carry out from MSB Position.
❖ The sum will be algebraically correct value in the representation if the range is in the -2n-1
through +2n-1-1.
❖ Subtraction
❖ To subtract two numbers X and Y (X-Y), nd the 2’s complement of Y and add it to the X.
❖ The result will be algebraically correct value in the representation if the range is in the -2n-1
through +2n-1-1.
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Addition and Subtraction
 Overflow in Integer Arithmetic
❖ In the 2’s complement the n bit can represent the values in the range of -2n-1 through +2n-1-1.
❖ When the result of the arithmetic operation is outside the representable range an arithmetic over ow
has occurred.
❖ While adding, the carry put from the MSB will serve as the over ow indicator.
❖ For example, when using 4 bit signed numbers, if we try to add the numbers+7 and 14, the output
sum vector, S. is 101 I, which is the code for =5, an in correct result.
❖ The carry-out signal from the MSB position is 0.
❖ Similarly, if we try to add-4 and -6, we get 0110, +6 another incorrect result, and in this case, the carry-
out signal is 1.
❖ Thus, over ow may occur if both summands have the same sign.
fl
fl
fl
 Addition and Subtraction Logic unit
❖ The logic expression for sum is can
be implemented with a 3- input
XOR gate.
❖ The c i+1 carry-out function is
implemented with a two-level
AND-OR logic circuit.
❖ A convenient symbol for the
complete circuit for a single stage
of addition, called a full adder (FA)
 Ripple Carry Adder
❖ A cascaded connection of n full adder blocks, can be
used to add two n-bit numbers.
❖ Since the carries must propagate, or ripple, through
this cascade, the con guration is called an n-bit ripple-
carry adder.
❖ The carry-in, c0, into the least-signi cant-bit (LSB)
position provides a convenient means of adding 1 to a
number.
❖ For instance, forming the 2's complement of a number
involves adding 1 to the 1's-complement of the
number.
❖ The carry signals are also useful for interconnecting k
adders to form an adder capable of handling input
numbers that are kn bits long.
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 Addition/Subtraction Logic Unit
❖ When the Add/Sub control line is set to 1, the
Y vector is 1's-complement (that is, bit
complemented) by the XOR gates and c0 is set
to 1 to complete the 2’s-complementation of Y.
❖ An XOR gate can be added to detect the
over ow condition cn XOR cn-1.
❖
fl
 Multiplication on Numbers

Register Con guration for Multiplication

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 Multiplication on Signed Numbers
❖ Booth Algorithm

Booth Recording Example

Booth Multiplier Recording Table

 Booth Multipliers
❖ The Booth algorithm has two attractive
features.
❖ It handles both positive and negative
multipliers uniformly.
❖ It achieves some ef ciency in the
number of additions required when the
multiplier has a few large blocks of 1s
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 Division

Circuit Arrangement for Binary Division

 Integer Division
❖ Restoring Method
Do the following n times:
1. Shift A and Q left one binary position.
2. Subtract M from A, and place the answer
back in A.
3. If the sign of A is 1, set qo to 0 and add M
back to A (that is, restore A); otherwise,
set qo to 1.
 Division
❖ Non-restoring Method:
Step 1: Do the following n times:
1. If the sign of A is 0, shift A and Q left
one bit position and subtract M from A;
otherwise, shift A and Q left and add M
to A.
2. Now, if the sign of A is 0, set qo to 1;
otherwise, set go to 0.
Step 2: If the sign of A is 1, add M to A.
 Summary

❖ Addition using FA and Ripple carry Adder

❖ Multiplication using booth Algorithm
❖ Division using Restoring and Non-restoring methods