Operating Systems - Unit-IV

Memory Management

February 23, 2024

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UNIT-IV Syllabus

Memory Management
Logical Vs Physical Address Space
Swapping
Contiguous Memory Allocation
Segmentation
Paging
Segmentation with Paging
Virtual Memory Management
Background
Demand Paging
Copy-on-Write
Page Replacement
Page Replacement Algorithms
Allocation of Frames
Thrashing
Virtual memory in Windows.
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 Memory Management Background

Background

Program must be brought (from disk) into memory and placed within
a process for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit only sees a stream of addresses + read requests, or
address + data and write requests
Register access in one CPU clock (or less)
Main memory can take many cycles, causing a stall
Cache sits between main memory and CPU registers
Protection of memory required to ensure correct operation

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 Memory Management Background

Base and Limit Registers

A pair of base and limit registers define the logical address space
CPU must check every memory access generated in user mode to be
sure it is between base and limit for that user

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 Memory Management Background

Hardware Address Protection

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 Memory Management Background

Address Binding

Programs on disk, ready to be brought into memory to execute form

an input queue
Without support, must be loaded into address 0000
Inconvenient to have first user process physical address always at
0000
How can it not be?
Further, addresses represented in different ways at different stages of
a program’s life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
Each binding maps one address space to another

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 Memory Management Background

Binding of Instructions and Data to Memory

Address binding of instructions and data to memory addresses can

happen at three different stages
Compile time: If memory location known a priori, absolute code can
be generated; must recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not
known at compile time
Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)

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 Memory Management Background

Multistep Processing of a User Program

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 Memory Management Background

Logical vs. Physical Address Space

The concept of a Logical address space that is bound to a separate

physical address space is central to proper memory management
Logical address – generated by the CPU; also referred to as virtual
address
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and
load-time address-binding schemes;
logical (virtual) and physical addresses differ in execution-time
address-binding scheme
Logical address space is the set of all logical addresses generated by
a program
Physical address space is the set of all physical addresses generated
by a program

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 Memory Management Background

Memory-Management Unit (MMU)

Hardware device that at run time maps virtual to physical address

Many methods possible, covered in the rest of this chapter
To start, consider simple scheme where the value in the relocation
register is added to every address generated by a user process at the
time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses; it never sees the real
physical addresses
Execution-time binding occurs when reference is made to location in
memory
Logical address bound to physical addresses

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 Memory Management Background

Dynamic relocation using a relocation register

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 Memory Management Background

Dynamic Linking

Static linking – system libraries and program code combined by the

loader into the binary program image
Dynamic linking –linking postponed until execution time
Small piece of code, stub, used to locate the appropriate
memory-resident library routine
Stub replaces itself with the address of the routine, and executes the
routine
Operating system checks if routine is in processes’ memory address
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries
Consider applicability to patching system libraries
Versioning may be needed
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 Memory Management Swapping

Swapping

A process can be swapped temporarily out of memory to a backing

store, and then brought back into memory for continued execution
Total physical memory space of processes can exceed physical memory
Backing store – fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these
memory images
Roll out, roll in – swapping variant used for priority-based scheduling
algorithms; lower-priority
process is swapped out so higher-priority process can be loaded and
executed
Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped System maintains a
ready queue of ready-to-run processes which have memory images
on disk
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 Memory Management Swapping

Swapping (Cont.)

Does the swapped out process need to swap back in to same physical
addresses?
Depends on address binding method
Plus consider pending I/O to / from process memory space
Modified versions of swapping are found on many systems (i.e.,
UNIX, Linux, and Windows)
Swapping normally disabled
Started if more than threshold amount of memory allocated
Disabled again once memory demand reduced below threshold

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 Memory Management Swapping

Schematic View of Swapping

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 Memory Management Swapping

Context Switch Time including Swapping

If next processes to be put on CPU is not in memory, need to swap

out a process and swap in target process
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of 50MB/sec
Swap out time of 2000 ms
Plus swap in of same sized process
Total context switch swapping component time of 4000ms (4 seconds)
Can reduce if reduce size of memory swapped – by knowing how
much memory really being used
System calls to inform OS of memory use via request memory() and
release memory()

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 Memory Management Swapping

Context Switch Time and Swapping (Cont.)

Other constraints as well on swapping

Pending I/O – can’t swap out as I/O would occur to wrong process
Or always transfer I/O to kernel space, then to I/O device
Known as double buffering, adds overhead
Standard swapping not used in modern operating systems
But modified version common
Swap only when free memory extremely low

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 Memory Management Swapping

Swapping on Mobile Systems

Not typically supported

Flash memory based
Small amount of space
Limited number of write cycles
Poor throughput between flash memory and CPU on mobile platform
Instead use other methods to free memory if low
iOS asks apps to voluntarily relinquish allocated memory
Read-only data thrown out and reloaded from flash if needed
Failure to free can result in termination
Android terminates apps if low free memory, but first writes
application state to flash for fast restart
Both OSes support paging as discussed below

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 Memory Management Contiguous Allocation

Contiguous Allocation

Main memory must support both OS and user processes

Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with interrupt
vector
User processes then held in high memory
Each process contained in single contiguous section of memory

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 Memory Management Contiguous Allocation

Contiguous Allocation (Cont.)

Relocation registers used to protect user processes from each other,

and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address
must be less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient and kernel
changing size

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 Memory Management Contiguous Allocation

Hardware Support for Relocation and Limit Registers

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 Memory Management Contiguous Allocation

Multiple-partition allocation

Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – block of available memory holes of various size are scattered
throughout memory
When a process arrives, it is allocated memory from a hole large
enough to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about
allocated partitions
free partitions (hole)

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 Memory Management Contiguous Allocation

Multiple-partition allocation

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 Memory Management Contiguous Allocation

Dynamic Storage-Allocation Problem

How to satisfy a request of size n from a list of free holes?

First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

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 Memory Management Contiguous Allocation

Fragmentation

External Fragmentation – total memory space exists to satisfy a

request, but it is not contiguous
Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used
First fit analysis reveals that given N blocks allocated, 0.5 N blocks
lost to fragmentation
1/3 may be unusable ->50-percent rule

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 Memory Management Contiguous Allocation

Fragmentation (Cont.)

Reduce external fragmentation by compaction

Shuffle memory contents to place all free memory together in one large
block
Compaction is possible only if relocation is dynamic, and is done at
execution time
I/O problem
Latch job in memory while it is involved in I/O
Do I/O only into OS buffers
Now consider that backing store has same fragmentation problems

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 Memory Management Segmentation

Segmentation

Memory-management scheme that supports user view of memory

A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

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 Memory Management Segmentation

User’s View of a Program

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 Memory Management Segmentation

Logical View of Segmentation

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 Memory Management Segmentation

Segmentation Architecture

Logical address consists of a two tuple:¡segment-number, offset¿,

Segment table – maps two-dimensional physical addresses; each table
entry has:
base – contains the starting physical address where the segments reside
in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment table’s
location in memory
Segment-table length register (STLR) indicates number of segments
used by a program;
segment number s is legal if s <STLR

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 Memory Management Segmentation

Segmentation Architecture (Cont.)

Protection
With each entry in segment table associate:
validation bit = 0 ->illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing occurs at
segment level
Since segments vary in length, memory allocation is a dynamic
storage-allocation problem
A segmentation example is shown in the following diagram

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 Memory Management Segmentation

Segmentation Hardware

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 Memory Management Paging

paging

Physical address space of a process can be noncontiguous; process is

allocated physical memory whenever the latter is available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
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 Memory Management Paging

Address Translation Scheme

Address generated by CPU is divided into:

Page number (p) – used as an index into a page table which contains
base address of each page in physical memory
Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

For given logical address space 2m and page size 2n

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 Memory Management Paging

Paging Hardware

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 Memory Management Paging

Paging Model of Logical and Physical Memory

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 Memory Management Paging

Paging Example

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 Memory Management Paging

Paging (Cont.)

Calculating internal fragmentation

Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
Process view and physical memory now very different
By implementation process can only access its own memory

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 Memory Management Paging

Free Frames

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 Memory Management Paging

Implementation of Page Table

Page table is kept in main memory

Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
In this scheme every data/instruction access requires two memory
accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of a special
fast-lookup hardware cache called associative memory or translation
look-aside buffers (TLBs)

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 Memory Management Paging

Implementation of Page Table (Cont.)

Some TLBs store address-space identifiers (ASIDs) in each TLB entry

– uniquely identifies
each process to provide address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access next
time
Replacement policies must be considered
Some entries can be wired down for permanent fast access

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 Memory Management Paging

Associative Memory

Associative memory – parallel search

Address translation (p, d)

If p is in associative register, get frame # out
Otherwise get frame # from page table in memory

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 Memory Management Paging

Paging Hardware With TLB

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 Memory Management Paging

Effective Access Time

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 Memory Management Paging

Memory Protection

Memory protection implemented by associating protection bit with

each frame to indicate if read-only or read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
“invalid” indicates that the page is not in the process’ logical address
space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel

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 Memory Management Paging

Valid (v) or Invalid (i) Bit In A Page Table

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 Memory Management Structure of page table

Structure of the Page Table

Memory structures for paging can get huge using straight-forward

methods
Consider a 32-bit logical address space as on modern computers
Page size of 4 KB (212 )
Page table would have 1 million entries (232 /212 )
If each entry is 4 bytes ->4 MB of physical address space / memory for
page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables

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 Memory Management Structure of page table

Hierarchical Page Tables

Break up the logical address space into multiple page tables

A simple technique is a two-level page table
We then page the page table

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 Memory Management Structure of page table

Two-Level Page-Table Scheme

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 Memory Management Structure of page table

Two-Level Paging Example

A logical address (on 32-bit machine with 1K page size) is divided
into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided
into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
Known as forward-mapped page table 50/93
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 Memory Management Structure of page table

Address-Translation Scheme

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 Memory Management Structure of page table

64-bit Logical Address Space

Even two-level paging scheme not sufficient

If page size is 4 KB (212 )
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like

Outer page table has 242 entries or 244 bytes

One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes
in size
And possibly 4 memory access to get to one physical memory location

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 Memory Management Structure of page table

Three-level Paging Scheme

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 Memory Management Structure of page table

Hashed Page Tables

Common in address spaces >32 bits

The virtual page number is hashed into a page table
This page table contains a chain of elements hashing to the same
location
Each element contains (1) the virtual page number (2) the value of
the mapped page frame (3) a pointer to the next element
Virtual page numbers are compared in this chain searching for a
match
If a match is found, the corresponding physical frame is extracted
Variation for 64-bit addresses is clustered page tables
Similar to hashed but each entry refers to several pages (such as 16)
rather than 1
Especially useful for sparse address spaces (where memory references
are non-contiguous and scattered)
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 Memory Management Structure of page table

Hashed Page Table

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 Memory Management Structure of page table

Inverted Page Table

Rather than each process having a page table and keeping track of all
possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns that
page
Decreases memory needed to store each page table, but increases
time needed to search the table when a page reference occurs
Use hash table to limit the search to one — or at most a few —
page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical address
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 Memory Management Structure of page table

Inverted Page Table Architecture

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 Virtual memory Management Background

Background

Code needs to be in memory to execute, but entire program rarely

used
Error code, unusual routines, large data structures
Entire program code not needed at same time
Consider ability to execute partially-loaded program
Program no longer constrained by limits of physical memory
Each program takes less memory while running ->more programs run
at the same time
Increased CPU utilization and throughput with no increase in response
time or turnaround time
Less I/O needed to load or swap programs into memory ->each user
program runs faster

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 Virtual memory Management Background

Background (Cont.)

Virtual memory – separation of user logical memory from physical

memory
Only part of the program needs to be in memory for execution
Logical address space can therefore be much larger than physical
address space
Allows address spaces to be shared by several processes
Allows for more efficient process creation
More programs running concurrently
Less I/O needed to load or swap processes

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 Virtual memory Management Background

Background (Cont.)

Virtual address space – logical view of how process is stored in

memory
Usually start at address 0, contiguous addresses until end of space
Meanwhile, physical memory organized in page frames
MMU must map logical to physical
Virtual memory can be implemented via:
Demand paging
Demand segmentation

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 Virtual memory Management Background

Virtual Memory That is Larger Than Physical Memory

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 Virtual memory Management Background

Virtual-address Space

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 Virtual memory Management Background

Shared Library Using Virtual Memory

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 Virtual memory Management Demand paging

Demand Paging

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 Virtual memory Management Demand paging

Basic Concepts

With swapping, pager guesses which pages will be used before

swapping out again
Instead, pager brings in only those pages into memory
How to determine that set of pages?
Need new MMU functionality to implement demand paging
If pages needed are already memory resident
No difference from non demand-paging
If page needed and not memory resident
Need to detect and load the page into memory from storage
Without changing program behavior
Without programmer needing to change code

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 Virtual memory Management Demand paging

Valid-Invalid Bit

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 Virtual memory Management Demand paging

Page Table When Some Pages Are Not in Main Memory

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 Virtual memory Management Demand paging

Page Fault

If there is a reference to a page, first reference to that page will trap

to operating system:
page fault
Operating system looks at another table to decide:
Invalid reference ->abort
Just not in memory
Find free frame
Swap page into frame via scheduled disk operation
Reset tables to indicate page now in memory set validation bit = v
Restart the instruction that caused the page fault

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 Virtual memory Management Demand paging

Steps in Handling a Page Fault

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 Virtual memory Management Demand paging

Aspects of Demand Paging

Extreme case – start process with no pages in memory

OS sets instruction pointer to first instruction of process,
non-memory-resident ->page fault
And for every other process pages on first access
Pure demand paging
Actually, a given instruction could access multiple pages ->multiple
page faults
Consider fetch and decode of instruction which adds 2 numbers from
memory and stores result back to memory
Pain decreased because of locality of reference
Hardware support needed for demand paging
Page table with valid / invalid bit
Secondary memory (swap device with swap space)
Instruction restart

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 Virtual memory Management Demand paging

Instruction Restart

Consider an instruction that could access several different locations

block move

auto increment/decrement location

Restart the whole operation?
What if source and destination overlap?

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 Virtual memory Management Demand paging

Performance of Demand Paging

Stages in Demand Paging (worse case)
1 Trap to the operating system
2 Save the user registers and process state
3 Determine that the interrupt was a page fault
4 Check that the page reference was legal and determine the location of
the page on the disk
5 Issue a read from the disk to a free frame:
a Wait in a queue for device until the read request is serviced
b Wait for the device seek and/or latency time
c Begin the transfer of the page to a free frame
6 While waiting, allocate the CPU to some other user
7 Receive an interrupt from the disk I/O subsystem (I/O completed)
8 Save the registers and process state for the other user
9 Determine that the interrupt was from the disk
10 Correct the page table and other tables to show page is now in memory
11 Wait for the CPU to be allocated to this process again
12 Restore the user registers, process state, and new page table, and then
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 Virtual memory Management Demand paging

Performance of Demand Paging (Cont.)

Three major activities

Service the interrupt – careful coding means just several hundred
instructions needed
Read the page – lots of time
Restart the process – again just a small amount of time
Page Fault Rate 0 <= p <= 1
if p = 0 no page faults
if p = 1, every reference is a fault
Effective Access Time (EAT)

EAT = (1 – p) x memory access+ p (page fault overhead + swap

page out + swap page in )

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 Virtual memory Management Demand paging

Demand Paging Example

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 Virtual memory Management Demand paging

Demand Paging Optimizations

Swap space I/O faster than file system I/O even if on the same device
Swap allocated in larger chunks, less management needed than file
system
Copy entire process image to swap space at process load time
Then page in and out of swap space
Used in older BSD Unix
Demand page in from program binary on disk, but discard rather than
paging out when freeing frame
Used in Solaris and current BSD
Still need to write to swap space
Pages not associated with a file (like stack and heap) – anonymous
memory
Pages modified in memory but not yet written back to the file system
Mobile systems
Typically don’t support swapping
Instead, demand page from file system and reclaim read-only pages
(such as code)
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 Virtual memory Management Copy-on-Write

Copy-on-Write

Copy-on-Write (COW) allows both parent and child processes to

initially share the same pages in memory
If either process modifies a shared page, only then is the page copied
COW allows more efficient process creation as only modified pages
are copied
In general, free pages are allocated from a pool of zero-fill-on-demand
pages
Pool should always have free frames for fast demand page execution
Don’t want to have to free a frame as well as other processing on page
fault
Why zero-out a page before allocating it?
vfork() variation on fork() system call has parent suspend and child
using copy-on-write address space of parent
Designed to have child call exec()
Very efficient
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 Virtual memory Management Copy-on-Write

Before Process 1 Modifies Page C

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 Virtual memory Management Copy-on-Write

After Process 1 Modifies Page C

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 Virtual memory Management Copy-on-Write

What Happens if There is no Free Frame?

Used up by process pages

Also in demand from the kernel, I/O buffers, etc
How much to allocate to each?
Page replacement – find some page in memory, but not really in use,
page it out
Algorithm – terminate? swap out? replace the page?
Performance – want an algorithm which will result in minimum number
of page faults
Same page may be brought into memory several times

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 Virtual memory Management Page replacement

Page Replacement

Prevent over-allocation of memory by modifying page-fault service

routine to include page replacement
Use modify (dirty) bit to reduce overhead of page transfers – only
modified pages are written to disk
Page replacement completes separation between logical memory and
physical memory – large virtual memory can be provided on a smaller
physical memory

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 Virtual memory Management Page replacement

Need For Page Replacement

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 Virtual memory Management Page replacement

Basic Page Replacement

1 Find the location of the desired page on disk

2 Find a free frame:
If there is a free frame, use it
If there is no free frame, use a page replacement algorithm to select a
victim frame
Write victim frame to disk if dirty
3 Bring the desired page into the (newly) free frame; update the page
and frame tables
4 Continue the process by restarting the instruction that caused the trap
Note now potentially 2 page transfers for page fault – increasing EAT

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 Virtual memory Management Page replacement

Page Replacement

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Page Replacement Algorithms

First In First Out Page replacement

Least Recently Used Page replacement
Least frequently Used Page replacement
Optimal Page replacement

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 Virtual memory Management Allocation of Frames

Allocation of Frames

Each process needs minimum number of frames

Example: IBM 370 – 6 pages to handle SS MOVE instruction:
instruction is 6 bytes, might span 2 pages
2 pages to handle from
2 pages to handle to
Maximum of course is total frames in the system
Two major allocation schemes
fixed allocation
priority allocation
Many variations

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 Virtual memory Management Allocation of Frames

Fixed Allocation

Equal allocation – For example, if there are 100 frames (after

allocating frames for the OS) and 5 processes, give each process 20
frames
Keep some as free frame buffer pool
Proportional allocation – Allocate according to the size of process
Dynamic as degree of multiprogramming, process sizes change

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 Virtual memory Management Allocation of Frames

Priority Allocation

Use a proportional allocation scheme using priorities rather than size

If process Pi generates a page fault,
select for replacement one of its frames
select for replacement a frame from a process with lower priority
number

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 Virtual memory Management Allocation of Frames

Global vs. Local Allocation

Global replacement – process selects a replacement frame from the

set of all frames; one process can take a frame from another
But then process execution time can vary greatly
But greater throughput so more common
Local replacement – each process selects from only its own set of
allocated frames
More consistent per-process performance
But possibly underutilized memory

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 Virtual memory Management Allocation of Frames

Non-Uniform Memory Access

So far all memory accessed equally

Many systems are NUMA – speed of access to memory varies
Consider system boards containing CPUs and memory, interconnected
over a system bus
Optimal performance comes from allocating memory “close to” the
CPU on which the thread is scheduled
And modifying the scheduler to schedule the thread on the same
system board when possible
Solved by Solaris by creating lgroups
Structure to track CPU / Memory low latency groups
Used my schedule and pager
When possible schedule all threads of a process and allocate all
memory for that process within the lgroup

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 Virtual memory Management Thrashing

Thrashing

If a process does not have “enough” pages, the page-fault rate is very
high
Page fault to get page
Replace existing frame
But quickly need replaced frame back
This leads to:
Low CPU utilization
Operating system thinking that it needs to increase the degree of
multiprogramming Another process added to the system
Thrashing - a process is busy swapping pages in and out

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 Virtual memory Management Thrashing

Thrashing (Cont.)

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 Virtual memory Management Thrashing

Demand Paging and Thrashing

Why does demand paging work?Locality model

Process migrates from one locality to another
Localities may overlap
Why does thrashing occur?sum of size of locality >total memory size
Limit effects by using local or priority page replacement

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 Virtual memory Management Virtual Memory in windows

Virtual Memory in windows

Uses demand paging with clustering. Clustering brings in pages

surrounding the faulting page
Processes are assigned working set minimum and working set
maximum
Working set minimum is the minimum number of pages the process is
guaranteed to have in memory
A process may be assigned as many pages up to its working set
maximum
When the amount of free memory in the system falls below a
threshold, automatic working set trimming is performed to restore the
amount of free memory
Working set trimming removes pages from processes that have pages
in excess of their working set minimum
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