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CLAT3 - Set B

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14 views3 pages

CLAT3 - Set B

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pw5908
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We take content rights seriously. If you suspect this is your content, claim it here.
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SRM Institute of Science and Technology

College of Engineering and Technology Mode of Exam


School of Computing OFFLINE
(Common to all Branches)
DEPARTMENT OF COMPUTING TECHNOLOGIES
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu

Academic Year: 2023-24 (ODD)

Test: CLAT3 Date: 8.11.2023


Course Code & Title: 21CSS201T / COA Duration: 100 minutes
Year & Sem: II & III SET B Max. Marks: 50
Course Articulation Matrix:
Course
Learning At the end of this course, learners will PO PO PO PO PO PO PO PO PO PO PO PO
Outcome be able to: 1 2 3 4 5 6 7 8 9 10 11 12
s (CLO)
Analyze concepts of parallelism and - - - - - - -
CO-4 H - - - -
multi-core processors
Classify the memory technologies,
- - - - - - -
CO-5 input-output systems and evaluate the H M - - -
performance of memory system

Part – A
Instructions: Answer all (10 x 1 = 10 Marks)

Q. Question Marks BL CO PO PI
No Code
1. The stages of 3 stage pipelining are ____. 1 1 4 1.3 1.3.1
a. Decode, Fetch, Execute
b. Execute, Fetch, Decode
c. Fetch, Decode, Execute
d. Address generation, Fetch, Execute.
2 R2out , Yin 1 2 4 1.3 1.3.1
R3out, Select Y, Add, Zin
Zout, R1in

The above sequence of opertations represents


a. R3=R1+R2
b. R1=R2+R3
c. R2=R1+R3
d. R3=R2-R1
3 The contention for the usage of hardware device is called 1 1 4 1.3 1.3.1
a. Data hazard
b. Instruction hazard
c. Structural hazard
d. Stall
4 The conditional branch instruction outcome can be predicted 1 1 4 1.3 1.3.1
before the execution by using a logic called
a. Branch prediction
b. Delayed branch
c. Structural hazard
d. Static prediction
5 Which addressing mode is capable of working without fetch 1 1 4 1.3 1.3.1
operation?
a. Register indirect
b. Direct
c. Indexed
d. Immediate
6 What is the primary challenge of parallel computing related to 1 1 5 1 2.1.2
shared resources?
a) Scalability
b) Data synchronization
c) Energy efficiency
d) Algorithm complexity
7 Which type of parallel system is typically used for tasks that involve 1 1 5 1 2.1.2
repetitive operations on large data sets, like graphics rendering or
scientific simulations?
a) SISD
b) SIMD
c) MIMD
d) MISD
8 In ARM assembly language, what instruction is commonly used for 1 1 5 1 2.1.2
transferring data between memory and registers?
a) ADD
b) MOV
c) SUB
d) CMP
9 What is the purpose of the I/O operations in ARM architecture? 1 1 5 1 2.1.2
a) To perform arithmetic calculations
b) To manage memory allocation
c) To interact with input and output devices
d) To control processor temperature
10 What type of instruction encoding does ARM7 architecture use? 1 1 5 1 2.1.2
a. Fixed-length instruction encoding
b. Variable-length instruction encoding
c. CISC (Complex Instruction Set Computer) encoding
d. VLIW (Very Long Instruction Word) encoding
Part – B
Instructions: Answer any 4 ( 4 x 4 = 16 Marks)

11 Draw the generation of End control signal for single bus structure 4 3 4 1.3 1.3.1
with proper expression.
12 Illustrate the impact of complex addressing mode on instruction 4 4 4 1.3 1.3.1
flow in the pipeline
13 What is the sequence of operations for the instruction? 4 1 4 1.3 1.3.1
Move R2,(R1)?
14 Differentiate the Memory mapped I/O and I/O mapped I/O 4 3 5 2 2.1.2
15 A CPU has 12 registers and uses 6 addressing modes. 4 5 5 2 2.1.2
RAM is 64K x 32. What is the maximum size of the op-code field
if the instruction has a register operand and a memory address
operand?
PART C
Instructions: Answer all (12 x 2 = 24 Marks)

16. A Write the sequence of control steps required for single bus structure 12 3 4 1.3 1.3.1
for following instructions.
a) Add the immediate number NUM to register R1.
b) Add the contents of memory location NUM to register R1
OR
16. B I1: MUL R2,R3,R4 12 3 4 1.3 1.3.1
I2: ADD R5,R2,R1
When the above instructions are executed parallel identify the
type of hazard occurs? Specify the hardware and software
solution for handling the hazard.
17 A. Imagine you are the lead architect at a tech company that 12 3 5 2 2.1.2
specializes in developing real-time weather simulation software.
The software needs to process vast amounts of data from various
sources, simulate weather patterns, and provide real-time
visualizations. To enhance the performance and reduce the time
taken for simulations, you are considering implementing parallel
processing techniques.

a. Identify the need for parallelism in this scenario. (2marks)


b. Which type(s) of parallelism would be most suitable for this
application and why? (2marks)
c. List two potential applications of parallelism in the weather
simulation software. (2marks)
d. Highlight two challenges you might face when implementing
parallelism in this context. (2marks)
e. Based on Flynn’s classification, which architecture would be
most appropriate for this software? Explain your choice. (4
marks)
OR

17 B Draw and explain the structure of ARM registers and processor 12 3 5 2 2.1.2
modes

*Performance Indicators are available separately for Computer Science and Engineering in AICTE examination reforms
policy.

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

Approved by the Audit Professor/Course Coordinator

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