Ch4 Modular Design of

Digital Circuits
Lecture 4: Memory RAM and ROM

Content Reference: M. Morris Mano, and Michael D. Ciletti, “Digital Design with an introduction to Verilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson, 2017
Note: Reference to images may be found as hyperlinks or in slide notes
What is in this lecture?
• Introduction
• Random-Access Memory
• Memory Decoding
• Read-Only Memory
Outline
Introduction
• Memory Unit: “A collection of cells capable of storing a large quantity
of binary information”
• Memory operations
• Write: The process of storing new information into memory
• Read: The process of transferring the stored information out of memory
• Types of memory
• Random Access Memory(RAM) [Write/Read]
• Read Only Memory(ROM) [Read Only]
Programmable Logic Device (PLD)
• Programmable Logic Device (PLD): An integrated circuit with internal logic
gates connected through electronic paths. The desired logic is obtained
by programing the device.
• Programming: The hardware procedure which specifies the bits that are
inserted into the hardware configuration
• Example procedure: Original device has all electronic paths connected via fuses,
fuses are blown during programing
• Examples:
• ROM
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)
• Field Programmable Gate Array (FPGA)
Array logic diagrams vs conventional logic
diagrams
• The new convention is used as PLD may have hundreds to millions of gates
interconnected. Array logic diagrams show the internal logic diagram of
such a device in a concise form.
• The input lines are drawn perpendicular to this single line and are
connected to the gate through internal fuses.

Conventional Symbol Array Logic Symbol

Random-Access Memory
• Random-Access Memory: “The architecture of memory is such that
information can be selectively retrieved from any of its internal
locations. The time it takes to transfer information to or from any
desired random location is always the same”
• Word: A group of bits
• It can represent a number, an instruction, one or more alphanumeric
character
• Mostly multiples of 8 bits (i.e. 1 byte = 8 bits)
• A memory unit stores binary information in words
Block diagram of a memory unit
• The n data input lines provide the input to be
stored in the memory.
• The n data output lines supply the information
coming out of memory.
• The k address lines specify the location of a
particular word in the memory.
• The two control inputs(read/write) specify the
direction of the information transfer.
Addressing
• Address: An identification number assigned to each word
• Address starting from 0 to (2k-1)require k address lines
• In general: 2k ≥ m , where m – total number of words
• Example:
• 1024 words require 10 address lines
• 230 words require 30 address lines
• An internal decoder accepts the address and opens the paths needed
to select the word
• When a word is read or written, the memory operates on all its bits
as a single unit
Letters that are used to refer to the number
of words or bytes
It is customary to refer to the number of words (or bytes) in memory
with one of the letters below.
• K (kilo) is equal to 210
• M (mega) is equal to 220
• G (giga) is equal to 230
Example: Consider, a memory of 1K words of 16 bits each.
• Since 1K = 1024 and 16 bits = 2 bytes
• The memory can accommodate 2×1024 bytes
= 2,048 bytes = 2K bytes
Write Operation
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data input
lines.
n data input lines
3. Activate the write input.
k address lines
Memory unit
Read 2k words
n bit per word
Write

n data output lines

Read Operation
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.

n data input lines

k address lines
Memory unit
Read 2k words
n bit per word
Write

n data output lines

Memory Chips with Single Read/Write

Memory Enable Read/Write Memory Operation

0 X None
1 0 Write to selected word
1 1 Read from selected word
n data input lines

k address lines
Memory unit
Enable 2k words
n bit per word
Write/Read

n data output lines

Timing Waveforms
• The CPU is usually synchronized by its own clock
• Memory does not have an internal clock. CPU needs to give control
inputs (read/write) long enough
• Times related to memory
• Access time: The time required to select a word and read it
• Cycle time: Time required to complete a write operation
• Thus, CPU should devote a number of cycles greater than
Access/Cycle time for a memory request
• That is, maximum(Access time, Cycle time) < n × (1/clock frequency)
where, 𝑛 ∈ ℕ
Example
• Clock frequency = 50 MHz (i.e. period = 20 ns)
• If access time and cycle time do not exceed 50 ns
• CPU should dedicate at least 2.5 cycles per request
Example (Write Cycle) cont…

Write Cycle
 Example (Write Cycle) cont…

Crossed lines
indicate possible
change in value

Write Cycle
 Example (Write Cycle) cont…

Address is
placed before
writing to avoid
overwriting
wrong address

Write Cycle
Example (Read Cycle) cont…

Read Cycle
Types of Integrated Circuit RAM
• Static RAM (SRAM)
• Stores using Latches
• Faster
• Dynamic RAM (DRAM)
• Stores using charges on capacitors provided inside the chip by MOS
transistors
• Stored charge needs to be refreshed
Memory Decoding
• Memory Decoding : The process of selecting the memory word
specified by the input address
• Internal construction of a RAM
• m words and n bits per word
• m × n binary storage cells and associated decoding circuits
• Binary storage cell is the basic building block of a memory unit
 Binary storage cell
• The cell is modeled with a SR latch with associated gates to form a D latch
• Actually, the cell is an electronic circuit with four to six transistors
Select

Select

S Output Input BC Output

Input

R Read/Write

Read/Write

Logic Diagram Block Diagram

 Binary storage cell cont…
• Select input enables the cell for reading or writing
• Read/write input determines the operation of the cell when it is selected
Select

Select

S Output Input BC Output

Input

R Read/Write

Read/Write
1-Read
Logic Diagram Block Diagram
0-Write
Logical Construction of a small RAM
In general a k × 2k decoder is
• RAM consists of four words of four needed
bits each
• Thus, 2 address lines and 4×4 = 16
binary cells
• Address lines go to decoder to
select a word
Select

Input BC Output

Read/Write
Binary storage cell
Coincident Decoding
• A k × 2k decoder requires,
• 2k AND gates with k inputs per gate (i.e. one AND gate per minterm)
• For k address bits two k/2 × 2k/2 decoders can be used instead of one
k × 2k decoder
• One decoder to select row another to select column
Example
• 1k word memory is constructed with two 5 × 32 decoders instead of
one 10 × 1024 decoder
• Five most significant bits go to X
• Five least significant bits go to Y
• AND gates reduced from 1024 to 64

Accessing address
404 (01100 10100)
Address Multiplexing
• DRAMs use less transistors than SRAMs
• DRAMs are cheaper to make
• DRAMs can hols chared for a while until refreshing is needed
• DRAMs consume less energy
• Thus, DRAMs are available in large size
• The word size of DRAM is mostly 1 bit
• Due to large size it uses address multiplexing
Address Multiplexing cont…
• Here, the X and Y addresses
are sent separately
• The registers make sure the
address is held
Address Multiplexing cont…
• Send in X address, RAS = 0
• Address saves in register
• RAS = 1 (row register locked)
Address Multiplexing cont…
• Send in Y address, CAS = 0
• Address saves in register
• CAS = 1 (column register
locked)
Address Multiplexing cont…
• Read/Write can be used as
needed
• Next memory operation can
take place
Read Only Memory
• A ROM is a memory device where the binary information is stored permanently.
• The binary information must be specified by the designer and is then embedded
in the unit.
• Non-Volatile: Once the pattern is established, it stays within the unit even the
power is turned off an on again.
Read Only Memory cont…
A block diagram of a ROM consisting of k inputs and n outputs is shown below. The
inputs provide the address for memory and the outputs give the data bits of the
stored word that is selected by the address.

2k x n ROM
Programing a ROM
• A programmable connections between two lines is equivalent to a switch that
can be altered to be either closed or open
• Crosspoint : The programmable connection between two lines
• One of the simplest technologies employs a fuse that normally connects the two
points, but is opened or “blown” by the application of a high‐voltage pulse into
the fuse
Programing a ROM cont…
The internal storage of a ROM can be specified by a truth table that shows the
word content in each address
Example: The word content of a 25 x 8 ROM is given by the truth table (partial)
shown in table below
Programing a ROM cont…
• Word can be programmed by blowing the fuse at zeros
• x to denotes a temporary connection (dot for a permanent )
Combinational Circuit Implementation using
ROM
• Decoder to generates 2k minterms from k inputs and used OR gates to sum the
minterms
• A ROM output can be used as the output variable of a Boolean expression
• Each OR gate can represent a Boolean function
Combinational Circuit Implementation using
ROM cont…
We can consider each output terminal of the ROM separately as different Boolean
expressions and program them in ROM

Output of
Boolean
expressions
Example
Program a ROM to output square of 3 bit number
Example cont…
Notice B1 = 0
Example cont…
Notice A0 = B0
Example cont…
Thus we only need remaining outputs.
Example cont…
8 × 4 RAM is needed
Example cont…

Block Diagram Truth Table

Types of ROM
• ROM (Read-Only Memory): Programmed by manufacturer (mask
programing) adds cost of programing (suitable for mass production).
Irreversible Programing.
• PROM (Programmable ROM): Programmed by blowing fuses. Irreversible
Programing.
• EPROM (Erasable PROM): Can be reprogramed exposing to UV
• EEPROM (Electrically Erasable PROM): Can be reprogramed electronically.
Subject to fatigue.
• Flash Memory: Like EEPROM it is can be electrically erased, also has
circuitry to erase blocks of memory. Subject to fatigue typically 105 block
cycles.
References
[1] M. Morris Mano, and Michael D. Ciletti, “Digital Design with an
introduction to Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson, 2017 – Chapter 7.1 to 7.3 & 7.5