Ch4 Modular Design of

Digital Circuits
Lecture 4: Memory and Programmable Logic

Content Reference: M. Morris Mano, and Michael D. Ciletti, “Digital Design with an introduction to Verilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson, 2017
Note: Reference to images may be found as hyperlinks or in slide notes
What is in this lecture?
• Introduction
• Programmable Logic Array
• Programmable Array Logic
• Sequential Programable Devices
Outline
Programmable Logic Device (PLD)
• Programmable Logic Device (PLD): An integrated circuit with internal logic
gates connected through electronic paths. The desired logic is obtained
by programing the device.
• Programming: The hardware procedure which specifies the bits that are
inserted into the hardware configuration
• Example procedure: Original device has all electronic paths connected via fuses,
fuses are blown during programing
• Examples:
• ROM
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)
• Field Programmable Gate Array (FPGA)
Programmable Logic Devices (PLDs)
• They are a
combination of
AND Gates and
OR gates
• They can be
classified into
three groups
Programmable Logic Array
A PLA differs from a PROM as it does not provide full decoding of the variables and
does not generate all the minterms by default
• The decoder is replaced by an array of AND gates which can be
programmed
• The product terms are connected via an array of OR gates which also
can be programmed
Programmable Logic Array- Diagram
Inputs go AND gates for
through buffer product terms
inverter
combinations

XOR gates for

complementing
(Select 1) if
OR Gates needed
Sum of = (AC+BC)’
products
Gates in a PLA
• The PLA is specified by,
• Number of inputs (n) = Number of buffer-inverter gates
• Number of product terms (k) = Number of AND gates
• Number of outputs (m) = Number of OR gates/ XOR gates
• Thus,
• 2n × k connections between inputs and AND gates
• k × m connections between AND and OR gates

• A typical integrated circuit PLA may have 16 inputs, 48 product terms, and eight
outputs
Programming a PLA
Programing can be done as,
• Mask programing (by manufacture)
• FPLA (Field‐Programmable Logic Array): Field programing with a
commercial hardware programmer
Objective during programming
• Minimize number of product terms
• Size of the product term does not matter
Example
Implement the following two Boolean functions with PLA,
𝐹1 𝐴, 𝐵, 𝐶 = ∑(0, 1, 2, 4)
𝐹2 𝐴, 𝐵, 𝐶 = ∑(0, 5, 6, 7)

BC BC
00 01 11 10 00 01 11 10
A A
0 1 1 1 0 1
1 1 1 1 1 1

𝐹1 𝐹2
Example cont…
The true or complement values of the functions can be simplified,

BC BC
00 01 11 10 00 01 11 10
A A
0 1 1 0 1 0 1 0 0 0
1 1 0 0 0 1 0 1 1 1

𝐹1 = (𝐴𝐶 + 𝐵𝐶 + 𝐴𝐵)′ 𝐹2 = 𝐴𝐶 + 𝐴𝐵 + 𝐴′ 𝐵 ′ 𝐶′

F1’ is found in the k-map as in this way more product terms are common
Example cont…
So the PLA programming table is,

Inputs Outputs
Product Term
A B C F1 (C) F2 (T)
1 𝐴𝐵 1 1 –
2 𝐴𝐶 1 – 1
3 𝐵𝐶 – 1 1
4 𝐴′ 𝐵 ′ 𝐶′ 0 0 0

“–” no connection (fuse is blow at input and complement)

“0” connected to complement of input (fuse is blow at buffer input)
“1” connected to buffer input of input (fuse is blow at complement of input)
Example cont…
So the PLA programming table is,

Inputs Outputs
Product Term
A B C F1 (C) F2 (T)
1 𝐴𝐵 1 1 – 1 1
2 𝐴𝐶 1 – 1 1 1
3 𝐵𝐶 – 1 1 1 –
4 𝐴′ 𝐵 ′ 𝐶′ 0 0 0 – 1

“–” no connection (fuse is blow at input and complement)

“1” connected to product term
Example cont…
So the PLA programming table is,

Inputs Outputs
Product Term
A B C F1 (C) F2 (T)
1 𝐴𝐵 1 1 – 1 1
2 𝐴𝐶 1 – 1 1 1
3 𝐵𝐶 – 1 1 1 –
4 𝐴′ 𝐵 ′ 𝐶′ 0 0 0 – 1

𝐹1 = (𝐴𝐶 + 𝐵𝐶 + 𝐴𝐵)′ 𝐹2 = 𝐴𝐶 + 𝐴𝐵 + 𝐴′ 𝐵 ′ 𝐶′
Example cont…
Minimum Number of Product Terms
• This is usually done with the help of minimum number of terms
computer‐aided design (CAD)
• K-map minimization may not always work
• Consider the outputs below
BC BC
00 01 11 10 00 01 11 10
A A
0 1 0 0 0 0 1 0 0 1
1 0 0 0 0 1 0 0 0 1

With k-map, F1 = A’B’C’ With k-map, F2 = BC’ + A’C’

Instead, a better solution is below,

F1 = A’B’C’ F2 = BC’ + A’B’C’

Programmable Array Logic
• Fixed: OR array
• Programmable: AND array
Because only the AND gates are programmable,
• PAL is easier to program than PLA
• PAL is not flexible as PLA
Programmable Array Logic
cont…
• Inputs are connected to
buffer-inverter combinations
Programmable Array Logic
cont…
• Inputs are connected to
buffer-inverter combinations
• Outputs are obtained
through AND-OR sections
Programmable Array Logic
cont…
• Inputs are connected to
buffer-inverter combinations
• Outputs are obtained
through AND-OR sections
• n wide sections: Each section
has a constant number (n) of
AND gates and one OR gate
Programmable Array Logic
cont…
• Inputs are connected to
buffer-inverter combinations
• Outputs are obtained
through AND-OR sections
• n wide sections: Each section
has a constant number (n) of
AND gates and one OR gate
• Outputs are sometimes
driven by three‐state buffers
or inverters
Programmable Array Logic
cont…
• The PAL shown has 4 inputs, 4
outputs, and 4 sections, each
consisting of an 3‐wide AND–OR
array. One of the outputs is
connected to a buffer–inverter
gate and then fed back
• A typical PAL shown has 8 inputs,
8 outputs, and 8 sections, each
consisting of an 8‐wide AND–OR
array.
Designing a PAL
• Product terms are not shared
• Each function can be simplified by itself (easier to design)
• If (product terms > section width)
• Need to use multiple sections for Boolean function
Exercise
Construct a PAL logic for the combinational circuit mentioned by below given
Boolean expressions

• 𝑤 𝐴, 𝐵, 𝐶, 𝐷 = ∑ 2, 12, 13
• 𝑥 𝐴, 𝐵, 𝐶, 𝐷 = ∑ 7, 8, 9, 10, 11, 12, 13, 14, 15
• 𝑦 𝐴, 𝐵, 𝐶, 𝐷 = ∑ 0, 2, 3, 4, 5, 6, 7, 8, 10, 11,15
• z 𝐴, 𝐵, 𝐶, 𝐷 = ∑(1, 2, 8, 12, 13)
Exercise cont…
Simplifying the four functions to a minimum number of terms results in,

• 𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵 ′ 𝐶𝐷′
• 𝑥 = 𝐴 + 𝐵𝐶𝐷
• 𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵 ′ 𝐷′
• 𝑧 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵 ′ 𝐶𝐷′ + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵 ′ 𝐶 ′ 𝐷

By using w, it is possible to reduce the number of terms for z from four to three
Exercise cont…
Simplifying the four functions to a minimum number of terms results in,

• 𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵 ′ 𝐶𝐷′
• 𝑥 = 𝐴 + 𝐵𝐶𝐷
• 𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵 ′ 𝐷′
• 𝑧 = 𝑤 + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵 ′ 𝐶 ′ 𝐷
 Product AND Inputs
Outputs
Term
Exercise cont… A B C D w
1 1 1 0 – –
2 0 0 1 0 – 𝑤 = 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶𝐷′
The PAL programming
3 – – – – –
table is filled like for PLA
4 1 – – – –
5 – 1 1 1 – 𝑥 = 𝐴 + 𝐵𝐶𝐷

6 – – – – –
7 0 1 – – –
8 – – 1 1 – 𝑦 = 𝐴′ 𝐵 + 𝐶𝐷 + 𝐵′ 𝐷′

9 – 0 – 0 –
10 – – – – 1
11 1 – 0 0 – 𝑧 = 𝑤 + 𝐴𝐶 ′ 𝐷′ + 𝐴′ 𝐵′ 𝐶 ′ 𝐷

12 0 0 0 1 –
Exercise cont…

As it ANDs input
and its complement
Example: A.A’=0
Sequential Programable Divices
• Combinational PLD only contain gates
• Sequential programmable devices include both gates and flip‐flops
• Sequential programmable devices are vendor specific
• Three major types of sequential programmable devices
• Sequential (or simple) programmable logic device (SPLD)
• Complex programmable logic device (CPLD)
• Field‐programmable gate array (FPGA)
Sequential Programmable Logic Device (SPLD)
• Sequential PLD is also known as Simple PLD
• The circuit has,
• Flip-flops (D or JK)
• AND-OR array (PLA or PAL)

Inputs AND-OR array

(PAL or PLA) Outputs
Flip-flops
Field‐Programmable Logic Sequencer (FPLS)
• FPLS is the first programmable device developed to support
sequential circuit
• Has a PLA with output driving flip-flops
• The flip-flop can operate as either JK or D type
• FPLS did not succeed as it has too many programable connections
Registered PALs
• The configuration mostly used in an SPLD is the combinational PAL
together with D flip‐flops
• PAL with flip-flops were known as registered PALs
• Each section was known as macrocell

Basic Macrocell logic

Macrocell
• Output is driven by an
edge‐triggered D flip‐flop
Macrocell cont…
• Output is driven by an
edge‐triggered D flip‐flop
• Output of the flip‐flop is
connected to a three‐state
buffer (or inverter)
controlled by OE
Macrocell cont…
• Output is driven by an
edge‐triggered D flip‐flop
• Output of the flip‐flop is
connected to a three‐state
buffer (or inverter) controlled
by OE
• Output of the flip‐flop is fed
back into one of the inputs
(present state)
Macrocell cont…
• Output is driven by an
edge‐triggered D flip‐flop
• Output of the flip‐flop is
connected to a three‐state
buffer (or inverter) controlled
by OE
• Output of the flip‐flop is fed
back into one of the inputs
(present state)
• A typical SPLD has from 8 to
10 macrocells
Macrocell cont…
• Output is driven by an
edge‐triggered D flip‐flop
• Output of the flip‐flop is
connected to a three‐state
buffer (or inverter) controlled
by OE
• Output of the flip‐flop is fed
back into one of the inputs
(present state)
• A typical SPLD has from 8 to 10
macrocells
• CLK and OE is common for all
flip-flops
Others features of a macrocell
• Ability to either use or bypass the flip‐flop
• Selection of clock edge polarity
• Preset and clear for the register
Complex Programmable Logic Device (CPLD)
• Design of a digital system using PLDs often requires the connection of
several devices to produce the complete specification
• CPLD is a collection of PLDs on a single IC with programmable
interconnection

General CPLD configuration

Complex Programmable Logic Device (CPLD)
cont…
• Input–Output (I/O) blocks provide the connections to the IC pins
• Three state buffers are used for the pins to act as input /output

General CPLD configuration

Complex Programmable Logic Device (CPLD)
cont…
• Input–Output (I/O) blocks provide the connections to the IC pins
• Three state buffers are used for the pins to act as input /output
• Input from (I/O) is transferred to switch and Output from switch to
(I/O) block

General CPLD configuration

Complex Programmable Logic Device (CPLD)
cont…
• Each PLD typically contains from 8 to 16 macrocells
• Unused product terms, they can be used by other nearby macrocells
• Flip‐flop is programmed to act as a D, JK, or T flip‐flop
Gate Array
• The basic component used in VLSI design
• Gare Array: Consists of a pattern of gates, fabricated in an area of
silicon, that is repeated thousands of times until the entire chip is
covered with gates
• Customer provide the manufacturer the desired interconnection
pattern
• First few levels of the fabrication process are common and
independent
Field‐Programmable Gate Array (FPGA)
• Consists,
• Array of millions of logic blocks
• Programmable input and output blocks
• A typical FPGA contains,
• Lookup tables (truth table in SRAM)
• Multiplexers
• Gates
• Flip‐flops
• Example of CMOS FPGA technology: Xilinx (AMD) FPGA, Altera (Intel)
FPGA
Using RAMs instead of ROMs
• Lookup tables use in SRAM
• Pro: Table can be programmed by writing into memory
• Con: Memory is volatile needs to be reloaded
• Reloading can be done by host computer or an onboard PROM
Computer‐aided design (CAD)
• The design with PLD, CPLD, or FPGA requires extensive CAD
• Tools available include,
• Hardware description languages (HDLs)
• Example: ABEL, VHDL, and Verilog
References
[1] M. Morris Mano, and Michael D. Ciletti, “Digital Design with an
introduction to Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson, 2017 – Chapter 7.6 to 7.7