CMOS Logic Gates

 Logic gates that are the basic building block of digital systems are created by
combining a number of n- and p-channel transistors.
 We have assumed positive logic.
 A MOSFET transistor is a voltage-controlled switch.
 The MOSFET acts as a switch and turns on or off depending upon the nature of the
input signal.
 There are two types of MOSFETs: NMOS and PMOS.
 The NMOS turns on when the voltage is high and off when the voltage is low.
 The PMOS, on the other hand, turns on whenever the voltage is low and goes off as
the voltage goes high.
 When the two are used together to realize the logic gates, they are called CMOS
(Complementary MOS) because NMOS and PMOS work in a complementary
fashion. When the NMOS switch turns on, the PMOS gets off, and vice-versa.
The CMOS Inverter or NOT Gate

 A NOT gate reverses the input logic state.

 The NOT gate shown below employing two series-connected enhancement-type
MOSFETS, one n-channel (NMOS) and one p-channel (PMOS).

Figure 1. A CMOS NOT gate.

 The input is connected to the gate terminal of the two transistors, and the output is
connected to both drain terminals.
 Applying +V (logic 1) to the input (Vi), transistor Q2 is “on,” and transistor Q1
remains “off.” Under this condition, the output voltage (Vo) is close to 0 V (logic 0).
 Connecting the input to ground (Vi = 0 V), transistor Q2 is “off,” and transistor Q1 is
“on.” Now, the output voltage is close to +V (logic 1).

A Y

0 1

1 0

Table 1. The truth table for a NOT circuit.

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The CMOS NAND Gate

NAND denotes NOT-AND.

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

Table 2. The truth table for a two-input NAND circuit.

 Figure 2 shows a CMOS two-input NAND gate.

 P-channel transistors Q1 and Q2 are connected in parallel between +V and the output
terminal.
 N-channel transistors Q3 and Q4 are connected in series between the output terminal
and ground.

Figure 2. A CMOS two-input NAND gate.

 With Q3 and Q4 transistors ”on” and Q1 and Q2 transistors “off,” the output is a logic
0. This condition happens when both inputs, A and B, are logic 1, confirming the
lowest row in the above truth table.
 With logic 0 in inputs A and B, Q3 and Q4 transistors are “off,” and Q1 and Q2
transistors are “on,” producing a logic 1 output. This is consistent with the first row of
the truth table.
 When one of the inputs is a logic “1” and the other one is a logic “0”, either Q3 is
“off” and Q2 is “on” or Q4 is “off” and Q1 is “on.” The output in both cases is a logic
“1,” validating the second and the third rows of the truth table.

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The NOR Gate

NOR signifies NOT-OR.

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

Table 3. The truth table for a two-input NOR circuit.

 The output of a NOR gate is logic 1 with logic 0 in both inputs. The outcomes for
other input combinations are logic 0.
 Figure 3 shows a CMOS two-input NOR gate.
 P-channel transistors Q1 and Q2 are connected in series between +V and the output
terminal.
 N-channel transistors Q3 and Q4 are connected in parallel between the output and
ground.

Figure 3. A CMOS two-input NOR gate.

 When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are
“off,” and the output is logic 1. This confirms the first row of the truth table above.
 With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a
logic 0 output that confirms the last row of the truth table.
 For the two remaining input combinations, either Q1 is “off” and Q3 is “on” or Q2 is
“off” and is Q4 “on”. In these cases, the output is logic 0 which is consistent with the
above truth table.

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The AND Gate

We can say that an AND gate is a NOT-NOT-AND or NOT-NAND. Then, it is just a NAND
gate followed by an inverter.

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

Table 4. The truth table for a two-input CMOS AND circuit.

Figure 4 shows a CMOS two-input AND gate.

Figure 4. A CMOS two-input AND gate.

The OR Gate
An OR gate is a NOT-NOT-OR or NOT-NOR. Then, it is a NOR gate followed by an
inverter.
Table 5 shows the truth table for the OR circuit.

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

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Figure 5. A CMOS two-input OR gate.

The Exclusive OR (XOR) Gate

The output of a two-input XOR circuit assumes the logic 1 state if one and only one input
assumes the logic 1 state.
An equivalent logic statement is: ”If B=1 and A=0, or if A=1 and B=0, then Y=1.”

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

Table 6. The truth table for a two-input XOR circuit.

Figure 6 shows a two-input logic diagram, and figure 7 shows a CMOS circuit to satisfy the
Boolean equation.

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Figure 6. A logic block diagram for the XOR circuit.

Figure 7. A CMOS two-input XOR gate.

 Transistors Q1, Q2, Q3, and Q4 comprise the NOR gate. Transistors Q5 and Q6 make
the ANDing of inputs A and B, and transistor Q7 supplies the ORing of the NOR
output with the ANDed output. Transistors Q8, Q9, and Q10 complement the
arrangement of transistors Q5, Q6, and Q7, inverting the result.

TTL vs. CMOS: Advantages and Disadvantages

 Since it appears that any gate possible to construct using TTL technology can be
duplicated in CMOS, why do these two “families” of logic design still coexist?
 The answer is that both TTL and CMOS have their own unique advantages.
 First and foremost on the list of comparisons between TTL and CMOS is the issue of
power consumption. In this measure of performance, CMOS is better. Because the
complementary P- and N-channel MOSFET pairs of a CMOS gate circuit are (ideally)
never conducting at the same time, there is little or no current drawn by the circuit
from the Vdd power supply except for what current is necessary to source current to a
load. TTL, on the other hand, cannot function without some current drawn at all
times, due to the biasing requirements of the bipolar transistors from which it is made.
 While the power dissipation of a TTL gate remains rather constant regardless of its
operating state(s), a CMOS gate dissipates more power as the frequency of its input
signal(s) rises. If a CMOS gate is operated in a static (unchanging) condition, it
dissipates zero power (ideally).
 CMOS gate circuits draw transient current during every output state switch from
“low” to “high” and vice versa. So, the more often a CMOS gate switches modes, the
more often it will draw current from the V dd supply, hence greater power dissipation
at greater frequencies.

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Advantages of CMOS
 A CMOS gate draws much less current from a driving gate output than a TTL gate
because MOSFETs are voltage-controlled, not current-controlled, devices. This
means that one gate can drive many more CMOS inputs than TTL inputs. The
measure of how many gate inputs a single gate output can drive is called fanout.
 CMOS has a much wider allowable range of power supply voltages. Whereas TTL
gates are restricted to power supply (Vcc) voltages between 4.75 and 5.25 volts,
CMOS gates are typically able to operate on any voltage between 3 and 15 volts!
 The reason behind this disparity in power supply voltages is the respective bias
requirements of MOSFET versus bipolar junction transistors. MOSFETs are
controlled exclusively by gate voltage (with respect to substrate), whereas BJTs
are current-controlled devices.
 TTL gate circuit resistances are precisely calculated for proper bias currents assuming
a 5 volt regulated power supply. Any significant variations in that power supply
voltage will result in the transistor bias currents being incorrect, which then results in
unreliable (unpredictable) operation.
 The only effect that variations in power supply voltage have on a CMOS gate is the
voltage definition of a “high” (1) state. For a CMOS gate operating at 15 volts of
power supply voltage (Vdd), an input signal must be close to 15 volts in order to be
considered “high” (1). The voltage threshold for a “low” (0) signal remains the same:
near 0 volts.
Disadvantages of CMOS
 CMOS is operating at a speed slower, as compared to TTL. The input capacitances of
a CMOS gate are much, much greater than that of a comparable TTL gate—owing to
the use of MOSFETs rather than BJTs—and so a CMOS gate will be slower to
respond to a signal transition (low-to-high or vice versa) than a TTL gate, all other
factors being equal.
 The RC time constant formed by circuit resistances and the input capacitance of the
gate tend to impede the fast rise- and fall-times of a digital logic level, thereby
degrading high-frequency performance.
Strategies to Combat the Disadvantages
 A strategy for minimizing this inherent disadvantage of CMOS gate circuitry is to
“buffer” the output signal with additional transistor stages, to increase the overall
voltage gain of the device. This provides a faster-transitioning output voltage (high-
to-low or low-to-high) for an input voltage slowly changing from one logic state to
another.