VLSI 4/M Laboratory Handout

CADENCE DESIGN
ENVIROMENT

I. Introduction
CMOS technology is prevalent in integrated circuit (IC) designs nowadays, due to the
wide availability of highly specified, low cost processes. Cadence is a popular industrial
design environment that provides designers an all-in-one tool to implement each stage
of the IC design and verification flows, as shown in Fig. 1.
The intention of this handout is to introduce new designers to the Cadence design
environment, and to describe all the steps for running the Cadence tools at the
Department of EE&E in the University of Glasgow. An operational trans-conductance
amplifier (OTA) is provided as an example to illustrate the entire design flow. At the
end of this lab, each designer is expected to implement each step of the example and
will be assessed according to their familiarity with the Cadence design environment and
the completeness of designing the example.

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 Figure 1. Analogue IC design flow and Cadence tools involved.

II. Setting up your Linux environment

1, Log in to the workstation
The Cadence design environment of this lab is a Linux-based software suite. Each
workstation in the lab-329 has Rocky Linux OS installed as dual boot option. Each
workstation is a terminal to the design environment, which means you can access your
saved works by using any of workstations in the lab. Please use your University account
username (email) or campus\GUID and password to log in. Note: This step is only
required if you are physically at the workstation and not remotely using a client.
2, Open a terminal

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Once logged in, you need to open a terminal to start the Cadence design environment.
On the upper left corner of the screen, you can select: Activities and from the dropdown
menu, select Terminal. Other applications such as web browser can be found under
Other Applications option.
3, Configure the system
Cadence design environment requires several application configuration files to work
properly. Using the command prompt: Make a working directory for Cadence project
mkdir your_directory_name Change to this directory

cd your_directory_name

Copy the cds.lib file that references the GPDK

cp /software/cadence-2019/cds.lib . Source

the settings file source /software/cadence-

2019/settings.bash Start virtuoso virtuoso &

The next time you start Cadence you DO NOT need to repeat all the steps, the steps
you need to perform next time are, 1. Change to your directory, 2. Source the settings
file and 3. Start virtuoso
Note: 1, Try to use any other keyword rather than “your_own_project_name”.

2, You only need to create a project folder when you start a design using a DIFFERENT process
technology. For existing designs or a new design using the same process technology, you can simply
use the folder you have created before.

After you have done all the required command lines above and with NO error message,
the Cadence Command Interpreter Window (CIW) and Library Manager Window
(LMW) should appear after a few seconds (If it takes a long time, please have a look at
the FAQs in page 16).
From the CIW menus in Fig. 3, all Cadence main tools and options can be accessed. In
the window area, all kinds of messages (info, errors, warnings, etc) generated by the
different Cadence tools appear. Therefore, it is RECOMMENDED to keep this window
on the top, so you can observe any response from the system after your action.
From the LMW in Fig. 4, it can be noted that libraries manage all the designs. Each
library contains cells and each cell contains different views. For example, different
kinds of amplifiers (common source stage, source follower, differential amplifier, etc)
can be stored as different cells in ONE library, named Amplifiers. Each of these
amplifier cells has different views, such as schematic, symbol, layout and extracted, to
represent the same amplifier under different occasions of usage.

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 Figure 3. Command Interpreter Window (CIW).

Figure 4. Library Manager Window.

III. Build your first design

According to the flow chart in Fig. 1, the first step of beginning a new design is to
compose a circuit schematic using the given specifications, which include power, speed,
area, gain and so on. In our example, a detailed design (an OTA) is provided, including
the circuit topology and parameters of the circuit. However, designers will have to use
their own designs instead in reality.
Firstly, a new library should be created to store your design. From Library Manager
Window,
a) Select File  New  Library. A new window appears, shown in Fig. 5(a).

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 b) Enter a library name, e.g., example, and click OK
c) Choose “Attach to an existing techfile”, as shown in Fig. 5(b) and click OK.
d) Choose “GPDK045” under Technology Library, as show in Fig. 5(c) and click
OK.

(a) (b)

(c)
Figure 5. Create a new library
Now, a new library named Amplifier should appear in the library manager list. This
library will use the transistors from the given technology. Next, we create a new cell
called OTA in the library Amplifier. A cell is a circuit to achieve targeted specifications.
It can be an amplifier, an inverter or a test circuit. One cell can be included into another
cell(s).

From the Library Manager window,

a) Select the library name that you just created, e.g., Amplifier
b) In library manager window, select File New  Cell View…
c) Enter a cell name, e.g., OTA

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d) Make sure the Library Name is Amplifier, View Name is schematic, and Tool
is Composer-Schematic, and click OK. A new blank schematic editor should
appear, shown in Fig. 6.

Figure 6. A new blank schematic editor

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 Figure 7. Provided OTA schematic
The next step is to add instances to your schematic. To add a new instance (any
component in the Cadence Environment is called instance), press instance button

on the top of the window as shown in Figure 8 at the top side of the window, or
press “i” on keyboard when “Cmd:” at the upper left-hand corner of the window is
empty.

Figure 8. Top view of schematic window

Otherwise, press “Esc” on your keyboard to exit any command mode.
A window should appear as shown below in Fig. 9.

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 (a)
Figure 9. Add a new instance.
Choose GPDK045 as your current library. For PMOS and NMOS transistors, select
pmos1v and nmos1v. Resistor, inductor and capacitor symbols can be found in
analogLib also supply nets and sources respectively.
Note: Single click on any instance you want to add, and single click again on the schematic
editing window to add it. Click and Drag will not work.

The command mode will change to “instance” when you want to add any instance. The
mode will shown at the upper left corner of the window. Press cancel in Fig. 8 or press
Esc on the keyboard to quit “instance mode” after you have finished adding all the
instances.

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 Figure 10. Property editing window.
There are six PMOS and four NMOS transistors needed to be added. The parameters of
these transistors are:
4 NMOS: Finger width=7.5µm, L=1.05µm and Fingers=1
4 smaller PMOS: Finger width=7.5µm, L=1.05µm and Fingers=2
2 bigger PMOS: Finger width=10µm, L=1.05µm and Fingers=2
To change the properties of each instance, select the instance (click on it until it is
highlighted) and press the property button on the right hand side of the window, or press
“q”, to open the property editor window, as shown below in Fig. 10.
Fig. 10. illustrates the parameters of one smaller PMOS transitor. There are three
parameters that can be adjusted in this example: Length, Finger width and Fingers and

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Multiplier. The number of fingers represents the number of transistors that have been
parallel connected by using only one instance symbol in the schematic. Hence a
transistor with Finger width of 7.5µm and 2 fingers will have a total width of 15µm.
Note: 1, Doing this results in better matching performance during layout and avoids
narrow/long layouts.

2, Do not change other parameters unless you know why you are doing so.

After you have added all the instances and adjusted all the parameters, some of the
instances may need to be rotated for a better connecting position. To rotate an instance,
choose Edit  Rotate, or press ‘r’ to obtain the rotate window. Choose one of the
options in rotate , sideways and upside down to rotate your instance. Try all of these
options to see the differences.
When all the instances are placed in the desired positions, you can start to wire them up.
To do so, select Wire (narrow) button on the left hand side of the window, or press ‘w’
to change command mode to “wire”. Firstly, click on the starting point, then RELEASE
the left mouse button, and click on the end point to finish. Press “Esc” to quit “wire
mode” after you finish adding the wires.
Pins define the input and output terminals of a circuit. To add a pin, click pin button at
the left hand side of the window, or press “p”. Enter a name for the pin and select
direction of a pin. In our example, the directions of all the pins except “out” are input.
Save and check (first button on the left hand side) your work after you have finished
the schematic. On CIW, it will inform you if there is any error or warning in your
schematic when you click “save and check”. Any error or warning will be highlighted
on schematic. Make sure there is NO warning or error before you proceed the next step.
The next step is to generate a new view for your schematic, called symbol. The reason
for doing so is that your cell may be repeatedly used as a block in other circuits. It is
better to hide the detail of your schematic to avoid any confusion, and easier to observe
and understand when used in a very large and complicated circuit. By using pins and a
symbol, a cell can be defined and used as a black box.
To add a symbol view to a circuit, select Create  Cellview  From Cellview. A new
window appears as below, Fig. 11, and click OK.

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 Figure 11. Create a symbol view.
Figure 12(a) shows the default view of the symbol. For an amplifier, it is normally
represented by a triangle. So, the drawing tools can be used to modify the default
symbol into Fig. 12(b).
Note: 1, RED box defines the boundary of the symbol, therefore CANNOT be deleted, the
green lines CAN be deleted and re-shaped to make the symbol as you want.

2, Put the pins (red square dots) ON the boundary.

3, DON’T delete the pins as this will result in an error of pin mismatch between schematic
and symbol view.

(a)

(b)

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 Figure 12. Symbol editing window.

V. Test your circuit.

To verify your amplifier, you need to compose a new test. Therefore, a new cell, named
OTAsim for example, can be created in the library Amplifier, to simulate the
functionality. The test schematic is shown below in Fig. 13.

Figure 13. OTA testing circuit.

The arrangement of the test circuit is a source follower (you can arrange the OTA into
other topologies for a test as well). Under a given biasing condition, the OTA will give
an identical output signal as its input, when a compatible load is attached.
Question:1, How to decide the biasing condition?

2, Which feature of the OTA will decide the compatibility of the load?

After the schematic is composed, you can begin to test your circuit by choosing Launch
 ADE. The Virtuoso Analogue Design Environment window should appear, as shown
in Fig. 14.
To test your schematic, three kinds of commonly used analyses can be applied. AC
analysis is normally used to test the frequency response of a circuit. DC analysis
normally tests the DC working point and behaviour of the circuit. Transient analysis
gives a time-based analysis, which is similar to the observations from an oscilloscope.

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In this example, a transient analysis is selected by Analysis  Choose, or press the
second button on the right hand side, then choose a proper start time, stop time and step
value (because computer simulations are based on discrete numerical computations, the
step value will determine the number of points for a wave form).

Figure 14. Virtuoso Analog Design Environment.

Choose Output  To be plotted  Select from schematic to pick up the signals to be
observed by clicking on the node wire. Then, chooses Simulation  Run or press the
“green light” button on the right-hand side of the window to run the simulation. The
simulation results should be similar as in Fig. 15.
FAQ: 1. Why does the CIW say the simulation is unsuccessful?

Choose Simulation  Output Log to see the reason. If it says that the Spectre has
not been checked out, then it is the simulator license problem. Otherwise, ask
demonstrator for help.

2. Why does it take a long time for me to start the Cadence environment after I
typed “virtuoso &” or my work can only be opened as read-only mode?

It may because you have typed “virtuoso &” more than once，or the Cadence has
not been closed properly at the last time.

a) Type “ps -e” in the terminal window to see all the processes running in the
system, then type “kill xxxx”, where XXXX represents the process ID (PID)
of virtuoso, to terminate all existing Cadence processes.
b) Go to your home folder from Linux menu bar and delete all files with
extension name of “.cdslck” in your home folder, your own project folder and
its sub folders.
c) In the terminal, type “virtuoso &” again under your own folder to start the
Cadence again.

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 “.cdslck” file is a temp file to store the current status of the Cadence environment.
It will be deleted automatically when Cadence is properly quitted.
If not, “.cdslck” file will be left in the working folder to represent that Cadence is
still running. This will lead to a conflict with a new Cadence process.

Figure 15. Simulation output waveforms.

VI. Layout your circuit.

The creation of the layout masks is one of the most important steps in the full-custom
(bottom-up) design flow, where the designer describes the detailed geometry and the
relative positioning of each mask layer to be used in actual fabrication, using Virtuoso
Layout Editor. Layout design is very tightly linked to overall circuit performances
(area, speed, accuracy and power dissipation), as the physical structures determine the
trans-conductance of the transistors, the parasitic capacitances and resistances, and
obviously, the silicon area that is used to realise a certain function. The physical (mask
layout) design is an iterative process, which starts with the circuit topology and initial
sizing of the transistors. It is extremely important that the layout design must not violate
any of the Layout Design Rules of the fabrication process, in order to ensure a high
probability of defect-free fabrication of all features described in the mask layout.
The detailed mask layout requires a very intensive and time-consuming design
effort, so that automated tools are employed as much as possible. Typically, the design
of digital circuits based on single-clock synchronous logic is completely automated.
First, a circuit description (typically in a hardware description language (HDL) as

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VHDL or Verilog) is synthesized, leading to a gate-level circuit description. From this
gate-level netlist, Place & Route programs automatically generate the layout. However,
analogy circuit designs are very sensitive to the layout style, so that an automated
procedure is normally difficult to implement. Usually a tedious, full-custom approach
is followed, where the designer manually builds the layout, basically drawing
rectangles of different layers.
After finishing the layout design, it is also important to Extract the netlist underlying
the layout view, for two main purposes:
a) This allows comparing it with the netlist extracted from the schematic. This
Layout versus Schematic (LVS) comparison ensures that the layout implements
the required functionalities.
b) If the extraction program also allows extracting parasitic capacitance and
resistance from the layout view, a more accurate, Post-Layout Simulation, can
be preformed taking into account the geometry of the circuit.
We will now create the layout view of the OTA example by using Virtuoso XL. After
opened the schematic view of the OTA in the library manager, you can click on Launch
 Layout XL to create a new layout view or opening an existing one as shown in
Figure 16.

Figure 16. Opening Layout XL.

To create a new layout view, make sure the Library Name and Cell Name are correct,
and View Name is layout and Tool is Virtuoso. To open an existing layout view of a
cell, you still need to make sure Library, Cell and View names before clicking OK.
A Virtuoso Layout Editor window with a Layer Selection Window (LSW) should
appear side by side with the schematic window, as shown in Fig. 17, if you are creating
a new layout view. Otherwise, you existing layout view will be opened.

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 (a)LSW

(b) Virtuoso Layout Editor Figure

17.
Because Layout XL automatically recognises all transistors and their connectivity, you
can add the layout of a transistor by selecting Connectivity Generate from Source
and a new window should appear as shown in Fig. 18.

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 Figure 18. Generate from Source.
It is noted that each layout instance is “linked” with its corresponding instance in the
schematic window. By clicking one, the other will be highlighted accordingly. The
suggested connection is indicated as well when you are dragging a transistor. To view
the contents of the instances, press “Shift + f”, to view only the bounding boxes again,
press “Ctrl +f”.

Figure 19. PMOS transistor showing bulk/body

Note: 1, CMOS transistors are symmetric devices, which means the source or drain of a
transistor totally depends on how the active region is connected. The indications
that you get when you are dragging a transistor are normally suggestions. You do
not HAVE TO follow them. They can be wrong occasionally.

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 2, DO NOT open a layout view by double clicking it from library manager, as it will lose
the connections between the schematic view and layout view for all transistors.

Each transistor picked up from schematic is a “package” of multiple mask layers which
are denoted by different colours. The bulk connection is not automatically added during
layout generation, but this can be included by editing the layout instance parameter for
body type as shown in Figure 20. Also, change the source/drain (S/D) metal width to
1µm.

Figure 20. Edit instance property to include the bulk/body

FAQ: Why is my PMOS longer than it is shown in the handout example?

Because in the handout, each of PMOS transistors is divided into two half-sized ones, and
parallelly connected to achieve a better matching performance. To do this, a)
Delete the PMOS you have added in layout, b) in schematic window, change the
width of your transistor to half the size and the number of fingers to 2, c) add
them again to the layout. You will get twice the number of PMOS when you verify
your layout using LVS later. The wider ones will have their DRAIN sheared (or
Source? Why?).

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 Figure 21. Connect gates of two PMOS transistors.
After adding all the transistors into the layout view with correct sizes, they should be
placed and wired up according to the schematic. Here is how:
a) To connect two or more nodes, which are using the SAME mask layer, you can
draw a “properly sized” rectangle box using the same layer in LSW, and make
them all “touch” with each other, as illustrated in Fig. 21 (The highlighted part
is the joint box using poly). Overlap is allowed but not compulsory.
b) To connect two nodes, which are using different mask layers, metal-1 layer is
always required. To connect an active layer or poly to metal-1: 1) draw a
metal-1 rectangle box on top of active area or poly, 2) add a contact on top of
the overlap area of these two layers by clicking Create  Via. A create contact
window will appear, choose proper Via Type, and Rows or Columns if an array
of contact is required. If two active areas are required to be connected, you can
use metal-1 to connect them.
c) One special case is that if two NMOS or PMOS have their source connected,
for example a differential pair or a current mirror, you can make a connection
by overlapping one of their active areas.
d) If more than one PMOS have their bulks connected, they can be placed in the
same nwell. Note, the size of poly and metal-1 etc should be equivalent or
larger than the corresponding size of the contact. It also applies for P-type
material as well.
As mentioned before, for the same circuit schematic, the layout can be different among
designers. If the layout can pass the Design Rule Check (DRC), Layout vs. Schematic
(LVS) and Post-layout simulation, it can be regarded as a “correct” one, even if it looks
significantly different from another “correct” one. However, this does not mean that
you can arbitrarily place components in different orientation on your layout. There are
certain rules to distinguish a good layout from a bad one. Figure 22 gives an example
layout implementation for the OTA.

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 Some general rules during layout design:

1, Use as few layers of metal as possible and try to avoid metal layer cross-over.
(Why?)

2, Do not orthogonally place the transistors, keep all the gates in one direction.

3, Use more than one contact to connect active region with metal layer if possible. (Why?)

4, Keep the area as small and square as possible.

5, Use wider metal layer for the power wires, such as VDD or VSS. (Why?)

Figure 22. An example layout implementation of the OTA.

During layout editing, it is RECOMMENDED to check the layout against design rules
using DRC check REGULARLY by selecting Assura  Run Assura DRC. The
correct path must be selected for the Assura DRC rules file (navigate to

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/software/cadence-2019/GPDK/gpdk045_v_6_0/assura/assuraDRC.rul). Results can
be observed from the DRC output file window after clicking OK in Fig. 23.

Figure
23.DRC.
FAQ: 1, There are some errors displayed in after I checked my layout using DRC. Why is
not highlighted in the layout? Or I cannot observe the errors that mentioned in
output log file.

Normally, DRC errors are highlighted on the layout view. It is possible that some errors
are really small in size and can hardly be observed from certain zoom size. All the
errors are highlighted using markers. Therefore, select the error from the output
file to zoom into the area where there is a DRC error.

A successful DRC check would return the window showed in Figure 24

Figure 24. DRC passed.

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 2, Why my transistors or other components cannot be placed in a line? Or there
are some errors in CIW that says some “grid” problem?

All the components are placed and aligned using grid control. Choose “Options
 Display” or press “e” to open Display Options window. On the upper right
corner, there is a section called Grid Controls. Choose Type = dots, Minor Spacing
= 1, Major Spacing = 5, X Snap Spacing = 0.15, Y Snap Spacing = 0.15, then Click
on Apply. The problem should be fixed now. If not, change X and Y Snap Spacing
to be 0.05.

VII. Verify your layout.

Finishing the entire layout can take a long time for new designers. It is normal for
everyone. However, enthusiasm, patient and carefulness are required for a new designer
to become an experienced one. DRC is the best “teacher” to check the entire sizing and
spacing mistakes. Once the new layout view passes the DRC check with no error or
warning, it is time to verify the connectivity by using LVS check. To perform this check,
click on AssuraRun Assura LVS. The LVS window shown below will appear to
allow you to set the paths for the extract rules and compare rules to enable a LVS check.

Figure 25. LVS.

A successful LVS check would result in the window shown in Figure 26(a). If not, you
can debug from the window shown in 26(b)

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 (a) (b)
Figure 26. LVS completed.
After a successful layout and checks, extraction must be done to enable the extraction
of parasitic capacitances and to generate an extracted view which would be used for
simulation to compare with the schematic simulation carried out earlier.
To perform an extraction, first select AssuraOpen Run to ensure the run name is the
name of your design and directory are the same as the one which you are currently
working usually indicated by a “.” in the run directory path DO NOT CHANGE
THIS TO SOMETHING DIFFERENT.

Figure 27. Open Run

Then open AssuraTechnology to include the path for assura technology library

Figure 28. Assura Technology Library Select

Figures 29(a) to (c) shows the parasitic extraction run form with tabs for setup,
extraction and netlisting to be completed.

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 (a) QRC setup.
For the QRC setup tab, the setup directory path must be set to typical as shown above
and the output set to extracted view.

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 (b) QRC extraction.
For the extraction form, the extraction type should be set to C only (Capacitance only)
and a reference node (vss) must be provided.

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 (c) QRC netlisting.
Figure 29. Parasitic extraction run form.
On the netlisting tab of the parasitic extraction form, the parasitic capacitor model must
be set to either include as comment or do not include. This would allow for successful
netlisting during the post layout simulation as Spectre does not have the model libraries
for the parasitic capacitors if you set this to include as model.
After setting up and click OK, a successful QRC extraction would display a window
indicating that an extracted view has been created in the library.

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 Figure 30. Extracted result

A new view named “av_extracted” should appear in the view list of the library manager.
Open this view by double clicking, the extracted view will appear and show all the
interconnections, recognised transistors and parasitic capacitances, as shown in

Figure 31. Extract view.

The Cadence has transferred the layout as another new netlist. Next step is to compare
it with the schematic design by performing a post -layout simulation.
Post-layout simulation will use the actual extracted layout netlist with the intrinsic
parasitic capacitors for the circuit simulation, rather than using the ideal schematic
netlist. Here is how:
a) Open the simulation schematic, as shown in Fig. 13.
b) Open the analogue environment, as shown in Fig. 14.
c) Choose Setup  Environment option and add av_extracted at the first place
in Switch View list, as shown in Fig. 32.
d) Click OK and run the simulation same again as before. If you get the same result
as previous one, congratulations, your design works. Otherwise, go back to
layout editor and think about if is there any possible parasitic capacitor

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 could short your circuit in some way, or is there any missed connection
compared to the schematic, etc.

Figure 32. Environment Options setting window.

Figure 33. Post layout simulation from extracted view.

Final steps would usually involve adding pads and sending to a foundry for fabrication,
but this is a process design kit for teaching and there is no foundry associated with it.

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Students are assessed individually using the following guide
questions
Name: Matric No.:

VLSI Design 4/M Laboratory Assessment

Take the Operational Trans-conductance Amplifier (OTA) in the laboratory
handout as an example; try to answer all the questions below:
1 Create a library called EXAM with the GPDK technology, create a cell called
Inverter and add a PMOS (30/1.05) and an NMOS (15/1.05). (1 mark)
2 Connect PMOS and NMOS as an inverter arrangement with Vdd = 1.5 V, perform
a DC analysis (from 0 - 1.5V at the input) and plot input and output on the same
graph. (2 marks)
3 Open your OTA schematic and explain:
a) What kind of input stage does the OTA have? Which transistors are they?
(1 mark)
b)Which part is the bias circuit? What kind of circuit topology it is? (1 mark)
c) Which part is the load of the circuit? Which transistors are they? (1 mark)
d)Which part is the second stage of the amplifier? Which transistors are
they? (1 mark)

4 How do you create a symbol of this circuit? Explain the steps and show your
symbol to the examiner. (1 mark)
5 Open the layout of the OTA using Layout XL, distinguish the schematic from the
layout, including 6 PMOS, 4NMOS, 6 PINs and all their connections. Explain
which parts are the bulks for the PMOS and NMOS, which type of layers are
they and why (2 marks). Use ‘ruler’ tool to show the size (L and W) of your
NMOS and PMOS? (1 mark)
6 What do DRC and LVS mean respectively? (1 mark) Why do we want these
checks? Please perform DRC and show the results in CIW. (3 marks if there is
no error or warning) Please perform LVS from the extracted view and show the
output log file. (3 marks if the number of nets, devices and terminals are
correct.)
7 Open the simulation circuit of this OTA (the source follower circuit). Perform a
TRANS analysis, show 3 sinusoid cycles for both input and output on the same
output graph using schematic netlist (1 mark) and extracted netlist (1 mark).

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