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
FEATURES DESCRIPTION
D 100 mΩ, 4.5-A Peak MOSFET Switch for High
Efficiency at 3-A Continuous Output Current The TPS54350 is a medium output current synchronous
D Uses External Lowside MOSFET or Diode buck PWM converter with an integrated high side
MOSFET and a gate driver for an optional low side
D Output Voltage Adjustable Down to 0.891 V
external MOSFET. Features include a high performance
With 1% Accuracy
voltage error amplifier that enables maximum
D Synchronizes to External Clock performance under transient conditions and flexibility in
D 1805 Out of Phase Synchronization choosing the output filter inductors and capacitors. The
D Wide PWM Frequency − Fixed 250 kHz, TPS54350 has an under-voltage-lockout circuit to prevent
500 kHz or Adjustable 250 kHz to 700 kHz start-up until the input voltage reaches 4.5 V; an internal
slow-start circuit to limit in-rush currents; and a power good
D Internal Slow Start
output to indicate valid output conditions. The
D Load Protected by Peak Current Limit and synchronization feature is configurable as either an input
Thermal Shutdown or an output for easy 180° out of phase synchronization.
D Adjustable Undervoltage Lockout
D 16-Pin TSSOP PowerPADE Package The TPS54350 device is available in a thermally
enhanced 16-pin TSSOP (PWP) PowerPAD package.
APPLICATIONS TI provides evaluation modules and the SWIFT Designer
D Industrial & Commercial Low Power Systems software tool to aid in quickly achieving high-performance
D LCD Monitors and TVs power supply designs to meet aggressive equipment
development cycles.
D Computer Peripherals
D Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
EFFICIENCY
Simplified Schematic
vs
Input LOAD CURRENT
TPS54350 Voltage 95
SYNC VIN
90
PWRGD 85
ENA
BOOT 80
Efficiency − %

VBIAS
PH 75
COMP Output
70
LSG Voltage
65
PGND
60 VI = 12 V
VSENSE
VO = 5 V
PWRPAD 55
fS = 250 kHz
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
IL − Load Current − A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
 
 
 !"#$%&'!$" !( )*%%+"' &( $# ,*-.!)&'!$" /&'+ %$/*)'( Copyright  2003 − 2004, Texas Instruments Incorporated
)$"#$% '$ (,+)!#!)&'!$"( ,+% '0+ '+%( $#
+1&( "('%*+"'( ('&"/&%/ 2&%%&"'3
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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION
TA OUTPUT VOLTAGE PACKAGE PART NUMBER
−40°C to 85°C Adjustable to 0.891 V Plastic HTSSOP (PWP) TPS54350PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS54350PWPR).

PACKAGE DISSIPATION RATINGS(1)

THERMAL IMPEDANCE TA = 25°C TA = 70°C TA = 85°C
PACKAGE
JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING
16-Pin PWP with solder(2) 42.1°C/W 2.36 1.31 0.95
16-Pin PWP without solder 151.9°C/W 0.66 0.36 0.26
(1) See Figure 46 for power dissipation curves.
(2) Test Board Conditions
1. Thickness: 0.062”
2. 3” x 3”
3. 2 oz. Copper traces located on the top and bottom of the PCB for soldering
4. Copper areas located on the top and bottom of the PCB for soldering
5. Power and Ground planes, 1 oz. Copper (0.036 mm thick)
6. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
7. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
VIN −0.3 V to 21.5 V
VSENSE −0.3 V to 8.0 V
UVLO −0.3 V to 8.0 V
Input voltage range, VI
SYNC −0.3 V to 4.0 V
ENA −0.3 V to 4.0 V
BOOT VI(PH) + 8.0 V
VBIAS −0.3 to 8.5 V
LSG −0.3 to 8.5 V
SYNC −0.3 to 4.0 V
Output voltage range, VO RT −0.3 to 4.0 V
PWRGD −0.3 to 6.0 V
COMP −0.3 to 4.0 V
PH −1.5 V to 22 V
PH Internally Limited (A)
Source current, IO LSG (Steady State Current) 10 mA
COMP, VBIAS 3 mA
SYNC 5 mA
LSG (Steady State Current) 100 mA
Sink current, IS PH (Steady State Current) 500 mA
COMP 3 mA
ENA, PWRGD 10 mA
Voltage differential AGND to PGND ±0.3 V
Operating virtual junction temperature range, TJ −40°C to +150°C
Storage temperature, Tstg −65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
Input voltage range, VI 4.5 20 V
Operating junction temperature, TJ −40 125 °C

ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Operating Current, PH Pin open,
5 mA
IQ Quiescent current No external low side MOSFET, RT = Hi-Z
Shutdown, ENA = 0 V 1.0 mA
Start threshold voltage 4.32 4.49 V
VIN Stop threshold voltage 3.69 3.97 V
Hysteresis 350 mV
UNDER VOLTAGE LOCK OUT (UVLO PIN)
Start threshold voltage 1.20 1.24 V
UVLO Stop threshold voltage 1.02 1.10 V
Hysteresis 100 mV
BIAS VOLTAGE (VBIAS PIN)
IVBIAS = 1 mA, VIN ≥ 12 V 7.5 7.8 8.0
VBIAS Output voltage V
IVBIAS = 1 mA, VIN = 4.5 V 4.4 4.47 4.5
REFERENCE SYSTEM ACCURACY
TJ = 25°C 0.888 0.891 0.894 V
Reference voltage
0.882 0.891 0.899 V
OSCILLATOR (RT PIN)
RT Grounded 200 250 300
Internally set PWM switching frequency kHz
RT Open 400 500 600
Externally set PWM switching frequency RT = 100 kΩ (1% resistor to AGND) 425 500 575 kHz
FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN)
SYNC out low-to-high rise time (10%/90%) (1) 25 pF to ground 200 500 ns
SYNC out high-to-low fall time (90%/10%) (1) 25 pF to ground 5 10 ns
Delay from rising edge to rising edge of
Falling edge delay time (1) 180 °
PH pins, see Figure 19
Minimum input pulsewidth (1) RT = 100 kΩ 100 ns
Delay (falling edge SYNC to rising edge PH) (1) RT = 100 kΩ 360 ns
50 kΩ resistor to ground, no pullup
SYNC out high level voltage 2.5 V
resistor
SYNC out low level voltage 0.6 V
SYNC in low level threshold 0.8 V
SYNC in high level threshold 2.3 V
Percentage of programmed frequency −10% 10%
SYNC in frequency range (1)
225 770 kHz
(1) Ensured by design, not production tested.

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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FEED− FORWARD MODULATOR (INTERNAL SIGNAL)
Modulator gain VIN = 12 V, TJ = 25°C 8 V/V
Modulator gain variation −25% 25%
Minimum controllable ON time (1) 180 ns
Maximum duty factor (1) VIN = 4.5 V 80% 86%
ERROR AMPLIFIER (VSENSE AND COMP PINS)
Error amplifier open loop voltage gain (1) 60 80 dB
Error amplifier unity gain bandwidth (1) 1.0 2.8 MHz
Input bias current, VSENSE pin 500 nA
COMP Output voltage slew rate (symmetric) (1) 1.5 V/µs
ENABLE (ENA PIN)
Disable low level input voltage 0.5 V
fs = 250 kHz, RT = ground (1) 4.6
Internal slow-start time (10% to 90%) ms
fs = 500 kHz, RT = Hi−Z (1) 2.3
Pullup current source 1.8 5 10 µA
Pulldown MOSFET II(ENA)=1 mA 0.1 V
POWER GOOD (PWRGD PIN)
Power good threshold Rising voltage 97%
fs = 250 kHz 4
Rising edge delay (1) ms
fs = 500 kHz 2
Output saturation voltage Isink = 1 mA, VIN > 4.5 V 0.05 V
PWRGD Output saturation voltage Isink = 100 µA, VIN = 0 V 0.76 V
Open drain leakage current Voltage on PWRGD = 6 V 3 µA
CURRENT LIMIT
Current limit VIN = 12 V 3.3 4.5 6.5 A
Current limit Hiccup Time (1) fs = 500 kHz 4.5 ms
THERMAL SHUTDOWN
Thermal shutdown trip point (1) 165 _C
Thermal shutdown hysteresis (1) 7 _C
LOW SIDE MOSFET DRIVER (LSG PIN)
Turn on rise time, (10%/90%) (1) VIN = 4.5 V, Capacitive load = 1000 pF 15 ns
Deadtime (1) VIN = 12 V 60 ns
VIN = 4.5 V sink/source 7.5
Driver ON resistance Ω
VIN = 12 V sink/source 5
OUTPUT POWER MOSFETS (PH PIN)
Phase node voltage when disabled DC conditions and no load, ENA = 0 V 0.5 V
VIN = 4.5 V, Idc = 100 mA 1.13 1.42
Voltage drop, low side FET and diode V
VIN = 12 V, Idc = 100 mA 1.08 1.38
VIN = 4.5 V, BOOT−PH = 4.5 V, IO = 0.5 A 150 300
rDS(ON), high side power MOSFET switch(2) mΩ
VIN = 12 V, BOOT−PH = 8 V, IO = 0.5 A 100 200
(1) Ensured by design, not production tested.
(2) Resistance from VIN to PH pins.

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PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)

VIN 1 16 BOOT
VIN 2 15 PH
UVLO 3 14 PH
PWRGD 4 THERMAL 13 LSG
RT 5 PAD 12 VBIAS
SYNC 6 11 PGND
ENA 7 10 AGND
COMP 8 9 VSENSE

NOTE: If there is not a Pin 1 indicator, turn device to enable

reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.

Terminal Functions
TERMINAL
DESCRIPTION
NO. NAME
1, 2 VIN Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor.
3 UVLO Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal
default VIN start and stop thresholds.
4 PWRGD Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage.
There is an internal rising edge filter on the output of the PWRGD comparator.
5 RT Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to
ground or floating will set the frequency to an internally preselected frequency.
6 SYNC Bidirectional synchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a
falling edge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock
by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the
Application Information section.
7 ENA Enable. Below 0.5 V, the device stops switching. Float pin to enable.
8 COMP Error amplifier output. Connect frequency compensation network from COMP to VSENSE pins.
9 VSENSE Inverting node error amplifier.
10 AGND Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.
11 PGND Power Ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Con-
nect to AGND and PowerPAD.
12 VBIAS Internal 8.0V bias voltage. A 1.0 uF ceramic bypass capacitance is required on the VBIAS pin.
13 LSG Gate drive for optional low side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency synchronous buck
converter configuration. Otherwise, leave open and connect schottky diode from ground to PH pins.
14, 15 PH Phase node—Connect to external L−C filter.
16 BOOT Bootstrap capacitor for high side gate driver. Connect 0.1 µF ceramic capacitor from BOOT to PH pins.
PowerPAD PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 21 for an example PCB
layout.

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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
BOOT

VIN PH
320 kΩ
Hiccup
UVLO UVLO Current Limit

125 kΩ 1.2V

SYNC
2x Oscillator
RT
Bias + Drive
PWM Ramp Regulator VBIAS
(FeedFoward)

S Q Adaptive Deadtime
PWM VBIAS
COMP Comparator and
Control Logic
VSENSE R LSG

VBIAS2 Error
Amplifier
Thermal
Reference Shutdown
System PWRGD
UVLO Rising
5 µA VSENSE
Edge
97% Ref UVLO
ENA Delay

Hiccup Hiccup
Timer

TPS54350

POWERPAD VBIAS PGND AGND

DETAILED DESCRIPTION
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) system has an internal accurate, but the absolute values of the internal resistors
voltage divider from VIN to AGND. The defaults for the may vary as much as 15%. If high accuracy is required for
start/stop values are labeled VIN and given in Table 1. The an externally adjusted UVLO threshold, select lower value
internal UVLO threshold can be overridden by placing an external resistors to set the UVLO threshold. Using a 1-kΩ
external resistor divider from VIN to ground. The internal resistor for the low side resistor (R2 see Figure 1) is
divider values are approximately 320 kΩ for the high side recommended. Under no circumstances should the UVLO
resistor and 125 kΩ for the low side resistor. The divider pin be connected directly to VIN.
ratio (and therefore the default start/stop values) is quite

Table 1. Start/Stop Voltage Threshold

START VOLTAGE THRESHOLD STOP VOLTAGE THRESHOLD
VIN (Default) 4.49 3.69
UVLO 1.24 1.02

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Input Voltage Supply

R1 320 kΩ

R2 1 kΩ 125 kΩ

Figure 1. Circuit Using External UVLO Function

The equations for selecting the UVLO resistors are: Extending Slow Start Time
VIN(start) 1 kW
R1 + * 1kW In applications that use large values of output capacitance
1.24 V (1)
there may be a need to extend the slow start time to
(R1 ) 1 kW) 1.02 V prevent the startup current from tripping the current limit.
VIN(stop) +
1 kW (2) The current limit circuit is designed to disable the high side
MOSFET and reset the internal voltage reference for a
For applications which require an undervoltage lock out
short amount of time when the high side MOSFET current
(UVLO) threshold greater than 4.49 V, external resistors
exceeds the current limit threshold. If the output
may be implemented, see Figure 1, to adjust the start
capacitance and load current cause the startup current to
voltage threshold. For example, an application needing an
exceed the current limit threshold, the power supply output
UVLO start voltage of approximately 7.8 V using the
will not reach the desied output voltage. To extend the slow
equation (1), R1 is calculated to the nearest standard
start time and to reduce the startup current, an external
resistor value of 5.36 kΩ. Using equation (2), the input
resistor and capcitor can be added to the ENA pin. The
voltage stop threshold is calculated as 6.48 V.
slow start capacitance is calculated using the following
Enable (ENA) and Internal Slow Start equation:
Once the ENA pin voltage exceeds 0.5 V, the TPS54350
starts operation. The TPS54350 has an internal digital CSS(µF) = 5.55e−3 Tss(ms)
slow start that ramps the reference voltage to its final value
The RSS resistor must be 2 kΩ and the slow start capacitor
in 1150 switching cycles. The internal slow start time (10%
must be less than 0.47 µF.
− 90%) is approximated by the following expression:

T + 1.15k Switching Frequency (RT)

SS_INTERNAL(ms) ƒ
s(kHz) (3)
The TPS54350 has an internal oscillator that operates at
Once the TPS54350 device is in normal regulation, the twice the PWM switching frequency. The internal oscillator
ENA pin is high. If the ENA pin is pulled below the stop frequency is controlled by the RT pin. Grounding the RT
threshold of 0.5 V, switching stops and the internal slow pin sets the PWM switching frequency to a default
start resets. If an application requires the TPS54350 to be frequency of 250 kHz. Floating the RT pin sets the PWM
disabled, use open drain or open collector output logic to switching frequency to 500 kHz.
interface to the ENA pin (see Figure 2). The ENA pin has
an internal pullup current source. Do not use external Connecting a resistor from RT to AGND sets the frequency
pullup resistors. according to the following equation (also see Figure 30).

RT(kW) + 46000
ƒ
s(kHz)–35.9 (4)

The RT pin controls the SYNC pin functions. If the RT pin

5 µA is floating or grounded, SYNC is an output. If the switching
frequency has been programmed using a resistor from RT
to AGND, then SYNC functions as an input.
Disabled RSS

CSS The internal voltage ramp charging current increases

Enabled
linearly with the set frequency and keeps the feed forward
modulator constant (Km = 8) regardless of the frequency
Figure 2. Interfacing to the ENA Pin set point.

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SWITCHING FREQUENCY SYNC PIN RT PIN

250 kHz, internally set Generates SYNC output signal AGND
500 kHz, internally set Generates SYNC output signal Float
Externally set to 250 kHz to 700 kHz Terminate to quiet ground R = 215 kΩ to 69 kΩ
with 10-kΩ resistor.
Externally synchronized frequency Synchronization Signal Use 110 kΩ when RT floats and 237 kΩ when RT is grounded and
using the sync out signal of another TPS54350. Set RT resistor
equal to 90% to 110% of external synchronization frequency.

1805 Out of Phase Synchronization (SYNC)

The SYNC pin is configurable as an input or as an output, phase, the total RMS input current is reduced. Thus
per the description in the previous section. When reducing the amount of input capacitance needed and
operating as an input, the SYNC pin is a falling-edge increasing efficiency.
triggered signal (see Figures 3, 4, and 19). When operating When synchronizing a TPS54350 to an external signal,
as an output, the signal’s falling edge is approximately the timing resistor on the RT pin must be set so that the
180° out of phase with the rising edge of the PH pins. Thus, oscillator is programmed to run at 90% to 110% of the
two TPS54350 devices operating in a system can share an synchronization frequency.
input capacitor and draw ripple current at twice the
frequency of a single unit. NOTE:
Do not use synchronization input for designs with
When operating the two TPS54350 devices 180° out of output voltages > 10 V.

VI(SYNC)

VO(PH)

Figure 3. SYNC Input Waveform

Internal Oscillator

VO(PH)

VO(SYNC)

Figure 4. SYNC Output Waveform

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Power Good (PWRGD) bandgap and scaling circuits are trimmed to produce
The VSENSE pin is compared to an internal reference 0.891 V at the output of the error amplifier, with the
signal, if the VSENSE is greater than 97% and no other amplifier connected as a voltage follower. The trim
faults are present, the PWRGD pin presents a high procedure improves the regulation, since it cancels offset
impedance. A low on the PWRGD pin indicates a fault. The errors in the scaling and error amplifier circuits.
PWRGD pin has been designed to provide a weak
PWM Control and Feed Forward
pull−down and indicates a fault even when the device is
unpowered. If the TPS54350 has power and has any fault Signals from the error amplifier output, oscillator, and
flag set, the TPS54350 indicates the power is not good by current limit circuit are processed by the PWM control
driving the PWRGD pin low. The following events, singly logic. Referring to the internal block diagram, the control
or in combination, indicate power is not good: logic includes the PWM comparator, PWM latch, and the
D VSENSE pin out of bounds
adaptive dead-time control logic. During steady-state
D Overcurrent operation below the current limit threshold, the PWM
D Thermal shutdown comparator output and oscillator pulse train alternately
D UVLO undervoltage reset and set the PWM latch.
D Input voltage not present (weak pull-down) Once the PWM latch is reset, the low-side driver and
D Slow-starting integrated pull-down MOSFET remain on for a minimum
D VBIAS voltage is low duration set by the oscillator pulse width. During this
Once the PWRGD pin presents a high impedance (i.e., period, the PWM ramp discharges rapidly to the valley
power is good), a VSENSE pin out of bounds condition voltage. When the ramp begins to charge back up, the
forces PWRGD pin low (i.e., power is bad) after a time low-side driver turns off and the high-side FET turns on.
delay. This time delay is a function of the switching The peak PWM ramp voltage varies inversely with input
frequency and is calculated using equation 5: voltage to maintain a constant modulator and power stage
gain of 8 V/V.
T + 1000 ms As the PWM ramp voltage exceeds the error amplifier
delay ƒ
s(kHz) (5) output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
Bias Voltage (VBIAS) FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low side gate driver. Up to During transient conditions, the error amplifier output can
1 mA of current can be drawn for use in an external be below the PWM ramp valley voltage or above the PWM
application circuit. The VBIAS pin must have a bypass peak voltage. If the error amplifier is high, the PWM latch
capacitor value of 1.0 µF. X7R or X5R grade dielectric is never reset and the high-side FET remains on until the
ceramic capacitors are recommended because of their oscillator pulse signals the control logic to turn the
stable characteristics over temperature. high-side FET off and the internal low-side FET and driver
on. The device operates at its maximum duty cycle until the
Bootstrap Voltage (BOOT) output voltage rises to the regulation set point, setting
VSENSE to approximately the same voltage as the
The BOOT capacitor obtains its charge cycle by cycle from
internal voltage reference. If the error amplifier output is
the VBIAS capacitor. A capacitor from the BOOT pin to the
low, the PWM latch is continually reset and the high-side
PH pins is required for operation. The bootstrap
FET does not turn on. The internal low-side FET and low
connection for the high side driver must have a bypass
side driver remain on until the VSENSE voltage decreases
capacitor of 0.1 µF.
to a range that allows the PWM comparator to change
states. The TPS54350 is capable of sinking current
Error Amplifier
through the external low side FET until the output voltage
The VSENSE pin is the error amplifier inverting input. The reaches the regulation set point.
error amplifier is a true voltage amplifier with 1.5 mA of
The minimum on time is designed to be 180 ns. During the
drive capability with a minimum of 60 dB of open loop
internal slow-start interval, the internal reference ramps
voltage gain and a unity gain bandwidth of 2 MHz.
from 0 V to 0.891 V. During the initial slow-start interval, the
Voltage Reference internal reference voltage is very small resulting in a
couple of skipped pulses because the minimum on time
The voltage reference system produces a precision causes the actual output voltage to be slightly greater than
reference signal by scaling the output of a temperature the preset output voltage until the internal reference ramps
stable bandgap circuit. During production testing, the up.

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Deadtime Control 100 ns, the ENA pin is pulled low, the high-side MOSFET
is disabled, and the internal digital slow-start is reset to 0 V.
Adaptive dead time control prevents shoot through current ENA is held low for approximately the time that is
from flowing in the integrated high-side MOSFET and the calculated by the following equation:
external low-side MOSFET during the switching
transitions by actively controlling the turn on times of the T + 2250
drivers. The high-side driver does not turn on until the HICCUP(ms) ƒ
s(kHz) (7)
voltage at the gate of the low-side MOSFET is below 1 V.
The low-side driver does not turn on until the voltage at the Once the hiccup time is complete, the ENA pin is released
gate of the high-side MOSFET is below 1 V. and the converter initiates the internal slow-start.
Setting the Output Voltage
Low Side Gate Driver (LSG)
The output voltage of the TPS54350 can be set by feeding
LSG is the output of the low-side gate driver. The 100-mA back a portion of the output to the VSENSE pin using a
MOSFET driver is capable of providing gate drive for most resistor divider network. In the application circuit of Figure
popular MOSFETs suitable for this application. Use the 24, this divider network is comprised of resistors R1 and
SWIFT Designer Software Tool to find the most R2. To calculate the resistor values to generate the
appropriate MOSFET for the application. Connect the LSG required output voltage use the following equation:
pin directly to the gate of the low-side MOSFET. Do not use
a gate resistor as the resulting turn-on time may be too R2 + R1 0.891
slow. V O * 0.891 (8)
Start with a fixed value of R1 and calculate the required R2
Integrated Pulldown MOSFET
value. Assuming a fixed value of 10 kΩ for R1, the
The TPS54350 has a diode-MOSFET pair from PH to following table gives the appropriate R2 value for several
PGND. The integrated MOSFET is designed for light−load common output voltages:
continuous−conduction mode operation when only an
OUTPUT VOLTAGE (V) R2 VALUE (KΩ)
external Schottky diode is used. The combination of
1.2 28.7
devices keeps the inductor current continuous under
conditions where the load current drops below the 1.5 14.7
inductor’s critical current. Care should be taken in the 1.8 9.76
selection of inductor in applications using only a low-side 2.5 5.49
Schottky diode. Since the inductor ripple current flows 3.3 3.74
through the integrated low-side MOSFET at light loads, the
inductance value should be selected to limit the peak Output Voltage Limitations
current to less than 0.3 A during the high-side FET turn off
time. The minimum value of inductance is calculated using Due to the internal design of the TPS54350 there are both
the following equation: upper and lower output voltage limits for any given input
voltage. Additionally, the lower boundary of the output
VO ǒ1 * VO
VI
Ǔ voltage set point range is also dependent on operating
frequency. The upper limit of the output voltage set point
L(H) +
ƒs 0.6 (6) is constrained by the maximum duty cycle of the device
and is shown in Figure 48. The lower limit is constrained
Thermal Shutdown by the minimum controllable on time which may be as high
as 220 ns. The approximate minimum output voltage for a
The device uses the thermal shutdown to turn off the given input voltage and range of operating frequencies is
MOSFET drivers and controller if the junction temperature shown in Figure 29 while the maximum operating
exceeds 165°C. The device is restarted automatically frequency versus input voltage for some common output
when the junction temperature decreases to 7°C below the voltages is shown in Figure 30.
thermal shutdown trip point and starts up under control of
The curves shown in these two figures are valid for output
the slow-start circuit.
currents greater than 0.5 A. As output currents decrease
Overcurrent Protection towards no load (0 A), the minimum output voltage
decreases. For applications where the load current is less
Overcurrent protection is implemented by sensing the than 100 mA, the curves shown in Figures 31 and 32 are
drain-to-source voltage across the high-side MOSFET applicable. All of the data plotted in these curves are
and compared to a voltage level which represents the approximate and take into account a possible 20 percent
overcurrent threshold limit. If the drain-to-source voltage deviation in actual operating frequency relative to the
exceeds the overcurrent threshold limit for more than intended set point.

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TYPICAL CHARACTERISTICS

LOOP RESPONSE LOAD REGULATION LINE REGULATION

60 180 0.2 0.10
50 150
1.5 A
40 Phase 120

Output Voltage Change − %

Output Voltage Change − %
3A
30 90 0.1 0.05
VI = 6 V
20 60 0A
G − Gain − dB

10 Gain 30
VI = 12 V
0 0 0.0 0.00
−10 −30
−20 VI = 12 V −60 VI = 18 V
VO = 3.3 V
−30 −90 −0.1 −0.05
IO = 3 A
−40 fS = 500 kHz −120
−50 See Figure 24 −150 See Figure 24 See Figure 24

−60 −180 −0.2 −0.10

10 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 6 8 10 12 14 16 18
f − Frequency − Hz IO − Output Current − A VI − Input Voltage − V

Figure 5 Figure 6 Figure 7

EFFICIENCY
vs
OUTPUT CURRENT INPUT RIPPLE VOLTAGE OUTPUT RIPPLE VOLTAGE
100

95 VI(Ripple) = 100 mV/div (ac coupled)

VO = 20 mV/div (ac)
VI = 6 V
90

85
Efficiency − %

80
Amplitude

Amplitude
75
VI = 12 V See Figure 24 V(PH) = 5V/div See Figure 24 V(PH) = 5 V/div
70

65 VI = 18 V
60 VO = 3.3 V
fS = 500 kHz
55
See Figure 24
50 VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IO − Output Current − A Time − 1 µs/div Time − 1 µs/div

Figure 8 Figure 9 Figure 10

PH PIN VOLTAGE LOAD TRANSIENT RESPONSE POWER UP

V(LSG) = 5 V/div VI = 12 V, VO = 3.3 V VI = 5 V/div

IO = 3 A, fS = 500 kHz
Load Transient Response − mV

See Figure 24
Power Up Waveforms − V

VO = 10 mV/div (ac coupled) VO = 2 V/div

Amplitude

See Figure 24 V(PH) = 5 V/div

V(PWRGD) = 2 V/div

IO = 1 A/div

See Figure 24
VI = 12 V, VO = 3.3 V, IO = 3 A, fS = 500 kHz

Time − 1 µs/div Time − 200 µs/div Time − 2 ms/div

Figure 11 Figure 12 Figure 13

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EFFICIENCY
vs
POWER DOWN OUTPUT CURRENT CONTINUOUS CONDUCTION MODE
100
VI = 5 V/div
95
VI = 6 V

Continuous Conduction Mode

Power Down Waveforms − V

90

VO = 2 V/div 85

Efficiency − %
80 V(PH) = 5 V/div
75
VI = 12 V
V(PWRGD) = 2 V/div 70
VI = 18 V
65
I(Inductor) = 0.5 A/div
60 VO = 3.3 V
fS = 500 kHz
See Figure 24 55
See Figure 25 See Figure 25
50
Time − 2 ms/div 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time − 1 µs/div
IO − Output Current − A

Figure 14 Figure 15 Figure 16

DISCONTINUOUS CONDUCTION MODE SEQUENCING WAVEFORMS INPUT RIPPLE CANCELLATION

V(PH1) = 10 V/div
VI = 10 V/div
Discontinuous Conduction Mode

Input Ripple Cancellation − V

Sequencing Waveforms − V

VO1 = 2 V/div
V(PH2) = 10 V/div

V(PH) = 5 V/div
V(PWRGD) = 2 V/div
VI(Ripple) = 100 mV/div (ac coupled)

VO2 = 2 V/div
I(Inductor) = 0.5 A/div V = 1.8 V, 3.3 V VIN = 12 V, VO1 = 1.8 V,
See Figure 25 See Figure 26 VO2 = 3.3 V, See Figure 26

Time − 1 µs/div Time − 2 ms/div Time − 1 µs/div

Figure 17 Figure 18 Figure 19

EFFICIENCY
vs
OUTPUT CURRENT
100

95

90

85
Efficiency − %

80

75

70

65
VI = 5 V
60 VO = −5 V
fS = 250 kHz
55
See Figure 27
50
0.0 0.5 1.0 1.5 2.0
IO − Output Current − A

Figure 20

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APPLICATION INFORMATION

VIN GND

VIN BOOT

VIN PH VOUT

UVLO PH

PWRGD LSG

RT VBIAS

SYNC PGND

ENA AGND
GND
COMP VSENSE

VIA to Ground Plane

Figure 21. TPS54350 PCB Layout

PCB LAYOUT
The VIN pins should be connected together on the printed copper. The length of the copper land pattern should be no
circuit board (PCB) and bypassed with a low ESR ceramic more than 0.2 inch.
bypass capacitor. Care should be taken to minimize the
loop area formed by the bypass capacitor connections, the For operation at full rated load, the analog ground plane
VIN pins, and the TPS54350 ground pins. The minimum must provide adequate heat dissipating area. A 3-inch by
recommended bypass capacitance is 10-µF ceramic with 3-inch plane of copper is recommended, though not
a X5R or X7R dielectric and the optimum placement is mandatory, dependent on ambient temperature and
closest to the VIN pins and the AGND and PGND pins. See airflow. Most applications have larger areas of internal
Figure 21 for an example of a board layout. The AGND and ground plane available, and the PowerPAD should be
PGND pins should be tied to the PCB ground plane at the connected to the largest area available. Additional areas
pins of the IC. The source of the low-side MOSFET and the on the bottom or top layers also help dissipate heat, and
anode of the Schottky diode should be connected directly any area available should be used when 3 A or greater
to the PCB ground plane. The PH pins should be tied operation is desired. Connection from the exposed area of
together and routed to the drain of the low-side MOSFET the PowerPAD to the analog ground plane layer should be
or to the cathode of the external Schottky diode. Since the made using 0.013-inch diameter vias to avoid solder
PH connection is the switching node, the MOSFET (or wicking through the vias. Four vias should be in the
diode) should be located very close to the PH pins, and the PowerPAD area with four additional vias outside the pad
area of the PCB conductor minimized to prevent excessive area and underneath the package. Additional vias beyond
capacitive coupling. The recommended conductor width those recommended to enhance thermal performance
from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce should be included in areas not under the device package.

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j0.0130
Minimum recommended thermal vias: 4 x
8 PL
.013 dia. inside powerpad area and
Minimum recommended exposed copper 4 x .013 dia. under device as shown.
area for powerpad. 5mm stencils may Additional .018 dia. vias may be used if top
side Analog Ground area is extended.
require 10 percent larger area.

0.0150
0.06

0.0371

0.0400

0.1970 0.1942 0.0400 0.0570

0.0400

0.0256
0.1700 Connect Pin 10 AGND
Minimum recommended top
and Pin 11 PGND to
side Analog Ground area. 0.1340
Analog Ground plane in
0.0690 this area for optimum
0.0400 performance.

Figure 22. Thermal Considerations for PowerPAD Layout

MODEL FOR LOOP RESPONSE

The Figure 23 shows an equivalent model for the The feed forward gain is modeled as an ideal voltage-
TPS54350 control loop which can be modeled in a circuit controlled voltage source with a gain of 8 V/V. The 1-mV
simulation program to check frequency response and ac voltage between nodes a and b effectively breaks the
dynamic load response. The error amplifier in the control loop for the frequency response measurements.
TPS54350 is a voltage amplifier with 80 dB (10000 V/V) of Plotting b/c shows the small-signal response of the power
open loop gain. The error amplifier can be modeled using stage. Plotting c/a shows the small-signal response of the
an ideal voltage-controlled current source as shown in frequency compensation. Plotting a/b shows the small-
Figure 23 with a resistor and capacitor on the output. The signal response of the overall loop. The dynamic load
TPS54350 device has an integrated feed forward response can be checked by replacing the RL with a
compensation circuit which eliminates the impact of the current source with the appropriate load step amplitude
input voltage changes to the overall loop transfer function. and step rate in a time domain analysis.
Rdc LO
a
PH
1 mV
ESR
R(switch) RL
b
CO
100 mΩ
+ + R1 R5
10 MΩ –
8 V/V TPS54350
– C8

VSENSE
– R2
+ 10 MΩ
+
10 MΩ + 0.891 R3
– 50 pF
20 V/V – 50 µA/V REF
C7
C6
COMP c

Figure 23. Model of Control Loop

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U1 L1
C3
TPS54350PWP 0.1 µF 10 µH
6 V − 18 V 1 2 VOUT 3.3 V @ 3 A
1 16
VIN BOOT
2 15 1 2 3 6 7
VIN PH
C1 C9 3 14 Q1
UVLO PH
47 µF 10 µF R4
4 13 4
PWRGD LSG 4.7 Ω
5 +
12 C2
RT VBIAS
100 µF
6 11
SYNC PGND
7 8 5
10 C4
ENA AGND C11
1 µF
8 9 3300 pF
COMP VSENSE
PWRPAD
17
C6
82 nF R3
768 Ω

C7 R1
1800 pF 1 kΩ

R5
Q1: Fairchild Semiconductor FDR6674A R2 137 Ω C8
L1: Vishay IHLP-5050CE 374 Ω 33 nF
C2: Sanyo 6TPC100M

Figure 24. Application Circuit, 12 V to 3.3 V

Figure 24 shows the schematic for a typical TPS54350 For this design example, use the following as the input
application. The TPS54350 can provide up to 3-A output parameters:
current at a nominal output voltage of 3.3 V. For proper DESIGN PARAMETER EXAMPLE VALUE
thermal performance, the exposed PowerPAD underneath Input voltage range 6 V to 18 V
the device must be soldered down to the printed circuit
Output voltage 3.3 V
board.
Input ripple voltage 300 mV
Output ripple voltage 30 mV
DESIGN PROCEDURE Output current rating 3A
Operating frequency 500 kHz
The following design procedure can be used to select NOTE: As an additional constraint, the design is set up to be small size
component values for the TPS54350. Alternately, the and low component height.
SWIFT Designer Software may be used to generate a
complete design. The SWIFT Designer Software uses an
SWITCHING FREQUENCY
iterative design procedure and accesses a comprehensive
database of components when generating a design. This The switching frequency is set using the RT pin.
section presents a simplified discussion of the design Grounding the RT pin sets the PWM switching frequency
process. to a default frequency of 250 kHz. Floating the RT pin sets
the PWM switching frequency to 500 kHz. By connecting
a resistor from RT to AGND, any frequency in the range of
DESIGN PROCEDURE 250 to 700 kHz can be set. Use equation 8 to determine the
proper value of RT.
To begin the design process a few parameters must be 46000
decided upon. The designer needs to know the following: RT(kW) +
ƒ s(kHz) * 35.9 (9)
D Input voltage range In this example circuit, RT is not connected and the
D Output voltage switching frequency is set at 500 kHz.

D Input ripple voltage

INPUT CAPACITORS
D Output ripple voltage
The TPS54350 requires an input decoupling capacitor
D Output current rating
and, depending on the application, a bulk input capacitor.
D Operating frequency The minimum value for the decoupling capacitor, C9, is

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10µF. A high quality ceramic type X5R or X7R is For this design example use KIND = 0.2 and the minimum
recommended. The voltage rating should be greater than inductor value is calculated to be 8.98 µH. The next highest
the maximum input voltage. Additionally some bulk standard value is 10 µH, which is used in this design.
capacitance may be needed, especially if the TPS54350
For the output filter inductor it is important that the RMS
circuit is not located within about 2 inches from the input
current and saturation current ratings not be exceeded.
voltage source. The value for this capacitor is not critical
The RMS inductor current can be found from equation 12:

Ǹ
but it also should be rated to handle the maximum input

ǒ Ǔ
voltage including ripple voltage and should filter the output 2

so that input ripple voltage is acceptable. V

OUT
ǒVIN(MAX) * VOUTǓ
I2
1
I + )
L(RMS) OUT(MAX) 12 V L F 0.8
IN(MAX) OUT SW
This input ripple voltage can be approximated by equation (13)

9:
and the peak inductor current can be determined with
ǒ Ǔ
I OUT(MAX) 0.25
DVIN + ) I OUT(MAX) ESR MAX equation 13:
C BULK ƒsw (10)
V
OUT
ǒVIN(MAX) * VOUTǓ
Where IOUT(MAX) is the maximum load current, ƒSW is the I L(PK) + I
OUT(MAX)
)
1.6 V IN(MAX) L F (14)
OUT SW
switching frequency, CBULK is the bulk capacitor value and
ESRMAX is the maximum series resistance of the bulk For this design, the RMS inductor current is 3.01 A and the
capacitor. peak inductor current is 3.34 A. The chosen inductor is a
Vishay IHLP5050CE-01 10 µH. It has a saturation current
The maximum RMS ripple current also needs to be
rating of 14 A and a RMS current rating of 7 A, easily
checked. For worst case conditions, this can be
meeting these requirements. A lesser rated inductor could
approximated by equation 10:
be used, however this device was chosen because of its
I low profile component height. In general, inductor values
OUT(MAX) for use with the TPS54350 are in the range of 6.8 µH to
I +
CIN 2 (11) 47µH.
In this case the input ripple voltage would be 140 mV and Capacitor Selection
the RMS ripple current would be 1.5 A. The maximum
The important design factors for the output capacitor are
voltage across the input capacitors would be VIN max plus
dc voltage rating, ripple current rating, and equivalent
delta VIN/2. The chosen bulk and bypass capacitors are
series resistance (ESR). The dc voltage and ripple current
each rated for 25 V and the combined ripple current
ratings cannot be exceeded. The ESR is important
capacity is greater than 3 A, both providing ample margin.
because along with the inductor current it determines the
It is very important that the maximum ratings for voltage
amount of output ripple voltage. The actual value of the
and current are not exceeded under any circumstance.
output capacitor is not critical, but some practical limits do
exist. Consider the relationship between the desired
closed loop crossover frequency of the design and LC
OUTPUT FILTER COMPONENTS
corner frequency of the output filter. In general, it is
Two components need to be selected for the output filter, desirable to keep the closed loop crossover frequency at
L1 and C2. Since the TPS54350 is an externally less than 1/5 of the switching frequency. With high
compensated device, a wide range of filter component switching frequencies such as the 500-kHz frequency of
types and values can be supported. this design, internal circuit limitations of the TPS54350
limit the practical maximum crossover frequency to about
Inductor Selection 50 kHz. Additionally, to allow for adequate phase gain in
the compensation network, the LC corner frequency
To calculate the minimum value of the output inductor, use
should be about one decade or so below the closed loop
equation 11:
crossover frequency. This limits the minimum capacitor

OUT(MAX)
V V
IN(MAX)
* V ǒ
OUT
Ǔ value for the output filter to:

L
MIN
+
V
IN(max)
K
IND
I
OUT
F
SW (12)
C
OUT
+ 1
LOUT
(2pƒK )CO
2
(15)
KIND is a coefficient that represents the amount of inductor Where K is the frequency multiplier for the spread between
ripple current relative to the maximum output current. For fLC and fCO. K should be between 5 and 15, typically 10 for
designs using low ESR output capacitors such as one decade difference.For a desired crossover of 50 kHz
ceramics, use KIND = 0.3. When using higher ESR output and a 10-µH inductor, the minimum value for the output
capacitors, KIND = 0.2 yields better results. capacitor is 100 µF. The selected output capacitor must be

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rated for a voltage greater than the desired output voltage When designing compensation networks for the
plus one half the ripple voltage. Any derating amount must TPS54350, a number of factors need to be considered.
also be included. The maximum RMS ripple current in the The gain of the compensated error amplifier should not be
output capacitor is given by equation 15: limited by the open loop amplifier gain characteristics and
should not produce excessive gain at the switching
ȡ VOUT ǒVIN(MAX) * VOUTǓ ȣ frequency. Also, the closed loop crossover frequency
ICOUT(RMS) + 1
Ǹ12 ȧVIN(MAX) LOUT FSW NCȧ should be set less than one fifth of the switching frequency,
Ȣ Ȥ(16) and the phase margin at crossover must be greater than
45 degrees. The general procedure outlined here
produces results consistent with these requirements
without going into great detail about the theory of loop
where NC is the number of output capacitors in parallel. compensation.

The maximum ESR of the output capacitor is First calculate the output filter LC corner frequency using
determined by the amount of allowable output ripple as equation 17:
specified in the initial design parameters. The output 1
ƒ +
ripple voltage is the inductor ripple current times the
ESR of the output filter so the maximum specified ESR
LC 2p LǸ C
OUT OUT (18)
as listed in the capacitor data sheet is given by equation
16: For the design example, fLC = 5033 Hz.

ǒ Ǔ
The closed loop crossover frequency should be greater
V IN(MAX) L
OUT
F
SW
0.8 than fLC and less than one fifth of the switching frequency.
ESR MAX + N DV p*p(MAX)
C
V
OUT
ǒVIN(MAX) * VOUTǓ Also, the crossover frequency should not exceed 50 kHz,
(17) as the error amplifier may not provide the desired gain. For
this design, a crossover frequency of 30 kHz was chosen.
Where nVp−p is the desired peak-to-peak output ripple. This value is chosen for comparatively wide loop
For this design example, a single 100-µF output capacitor bandwidth while still allowing for adequate phase boost to
is chosen for C2 since the design goal is small size. The insure stability.
calculated RMS ripple current is 156 mV and the maximum
ESR required is 59 mΩ. A capacitor that meets these Next calculate the R2 resistor value for the output voltage
requirements is a Sanyo Poscap 6TPC100M, rated at of 3.3 V using equation 18:
6.3 V with a maximum ESR of 45 mΩ and a ripple current
R2 + R1 0.891
rating of 1.7 A. An additional small 0.1-µF ceramic bypass
V * 0.891
capacitor is also used. OUT (19)
Other capacitor types work well with the TPS54350, For any TPS54350 design, start with an R1 value of 1.0 kΩ.
depending on the needs of the application. R2 is then 374 Ω.
Now the values for the compensation components that set
the poles and zeros of the compensation network can be
COMPENSATION COMPONENTS calculated. Assuming that R1 > R5 and C6 > C7, the pole
and zero locations are given by equations 19 through 22:
The external compensation used with the TPS54350
allows for a wide range of output filter configurations. A ƒ + 1
Z1 2pR3C6 (20)
large range of capacitor values and types of dielectric are
supported. The design example uses type 3 compensation 1
consisting of R1, R3, R5, C6, C7 and C8. Additionally, R2 ƒ +
Z2 2pR1C8 (21)
along with R1 forms a voltage divider network that sets the
output voltage. These component reference designators 1
ƒ +
are the same as those used in the SWIFT Designer P1 2pR5C8 (22)
Software. There are a number of different ways to design
a compensation network. This procedure outlines a ƒ + 1
P2 2pR3C7 (23)
relatively simple procedure that produces good results
with most output filter combinations. Use of the SWIFT Additionally there is a pole at the origin, which has unity
Designer Software for designs with unusually high closed gain with the following frequency:
loop crossover frequencies, low value, low ESR output
capacitors such as ceramics or if the designer is unsure ƒ + 1
about the design procedure is recommended. INT 2pR1C6 (24)
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This pole is used to set the overall gain of the compensated BIAS AND BOOTSTRAP CAPACITORS
error amplifier and determines the closed loop crossover
frequency. Since R1 is given as 1 kΩ and the crossover Every TPS54350 design requires a bootstrap capacitor,
frequency is selected as 30 kHz, the desired fINT can be C3 and a bias capacitor, C4. The bootstrap capacitor must
calculated with equation 24: be 0.1 µF. The bootstrap capacitor is located between the
PH pins and BOOT pin. The bias capacitor is connected
10–0.9 ƒ between the VBIAS pin and AGND. The value should be
ƒ + CO 1.0 µF. Both capacitors should be high quality ceramic
INT 2 (25)
types with X7R or X5R grade dielectric for temperature
And the value for C6 is given by equation 25: stability. They should be placed as close to the device
connection pins as possible.
C6 + 1 LOW-SIDE FET
2pR1ƒ
INT (26)
The TPS54350 is designed to operate using an external
The first zero, fZ1 , is located at one half the output filter LC low-side FET, and the LSG pin provides the gate drive
corner frequency, so R3 can be calculated from: output. Connect the drain to the PH pin, the source to
PGND, and the gate to LSG. The TPS54350 gate drive
1 circuitry is designed to accommodate most common
R3 +
pC6ƒ n-channel FETs that are suitable for this application. The
LC (27)
SWIFT Designer Software can be used to calculate all the
The second zero, fZ2 , is located at the output filter LC design parameters for low-side FET selection. There are
corner frequency, so C8 can be calculated from: some simplified guidelines that can be applied that
produce an acceptable solution in most designs.
C8 + 1 The selected FET must meet the absolute maximum
2pR1ƒ ratings for the application:
LC (28)

The first pole, fP1, is located to coincide with the output Drain-source voltage (VDS) must be higher than the
filter ESR zero frequency. This frequency is given by: maximum voltage at the PH pin, which is VINMAX + 0.5 V.
Gate-source voltage (VGS) must be greater than 8 V.
ƒ + 1
ESR 2pR C Drain current (ID) must be greater than 1.1 x IOUTMAX.
ESR OUT (29)
Drain-source on resistance (rDSON) should be as small as
where RESR is the equivalent series resistance of the possible, less than 30 mΩ is desirable. Lower values for
output capacitor. rDSON result in designs with higher efficiencies. It is
important to note that the low-side FET on time is typically
In this case, the ESR zero frequency is 35.4 kHz, and R5
longer than the high-side FET on time, so attention paid to
can be calculated from:
low-side FET parameters can make a marked
1 improvement in overall efficiency.
R5 +
2pC8 ƒ Total gate charge (Qg) must be less than 50 nC. Again,
ESR (30)
lower Qg characteristics result in higher efficiencies.
The final pole is placed at a frequency above the closed
Additionally, check that the device chosen is capable of
loop crossover frequency high enough to not cause the
dissipating the power losses.
phase to decrease too much at the crossover frequency
while still providing enough attenuation so that there is little For this design, a Fairchild FDR6674A 30-V n-channel
or no gain at the switching frequency. The fP2 pole location MOSFET is used as the low-side FET. This particular FET
for this circuit is set to 4 times the closed loop crossover is specifically designed to be used as a low-side
frequency and the last compensation component value C7 synchronous rectifier.
can be derived as follows:
POWER GOOD
C7 + 1 The TPS54350 is provided with a power good output pin
8pR3ƒ PWRGD. This output is an open drain output and is
CO (31)
intended to be pulled up to a 3.3-V or 5-V logic supply. A
Note that capacitors are only available in a limited range 10-kΩ, pull-up resistor works well in this application. The
of standard values, so the nearest standard value has absolute maximum voltage is 6 V, so care must be taken
been chosen for each capacitor. The measured closed not to connect this pull-up resistor to VIN if the maximum
loop response for this design is shown in Figure 5. input voltage exceeds 6 V.

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SNUBBER CIRCUIT amplitude of the ringing depends to a large degree on

R4 and C11 of the application schematic in Figure 24 parasitic effects, it is best to choose these component
comprise a snubber circuit. The snubber is included to values based on actual measurements of any design
reduce over-shoot and ringing on the phase node when the layout. See literature number SLUP100 for more detailed
internal high-side FET turns on. Since the frequency and information on snubber design.
U1 L1
C3
TPS54350PWP 0.1 µF 10 µH
6 V − 18 V 1 2 VOUT 3.3 V @ 3 A
1 16
VIN BOOT
2 15
VIN PH
C1 C9 3 14
UVLO PH
47 µF 10 µF R4
4 13
PWRGD LSG 4.7 Ω
5 +
12 D1 C2
RT VBIAS
100 µF
6 11
SYNC PGND
7 10 C4
ENA AGND
1 µF C11
8 9
COMP VSENSE 3300 pF
PWRPAD
17
C6
82 nF R3
768 Ω

C7 R1
1800 pF 1 kΩ

R5
D1: On Semiconductor MBRS340T3 R2 137 Ω C8
L1: Vishay IHLP-5050CE 374 Ω 33 nF
C2: Sanyo 6TPC100M

Figure 25. 3.3-V Power Supply With Schottky Diode

Figure 25 shows an application where a clamp diode is circuit remains operating in continuous mode during light
used in place of the low-side FET. The TPS54350 load operation. A 3-A, 40-V Schottky diode such as the
incorporates an integrated pull-down FET so that the Motorola MBRS340T3 or equivalent is recommended.

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U1 L1
C3
TPS54350PWP 0.1 µF 10 µH
6 V − 18 V VOUT 3.3 V @ 3 A
1 16 1 2
VIN BOOT
2 15 1 2 3 6 7
C9 VIN PH
+
C1 10 µF 3 14 Q1
UVLO PH
47 µF R10
Power Good 3.3 V 4 13 4
PWRGD LSG 4.7 Ω
5 +
12 C2
RT VBIAS
6 11 100 µF
SYNC PGND
7 8 5
10 C4
ENA AGND
8 1 µF C10
9 3300 pF
COMP VSENSE
PWRPAD
17
C6
82 nF R3
768 Ω
Pull up to 3.3 V or 5 V
C7 R1
1800 pF 1 kΩ

R5
R2 137 Ω C8
R4 33 nF
10 kΩ 374 Ω

Power Good 1.8 V

U2 L2
C5
TPS54350PWP 0.1 µF 10 µH
VOUT 1.8 V @ 3 A
1 16 1 2
VIN BOOT
2 15 1 2 3 6 7
VIN PH
C18 C15 3 14 Q2
UVLO PH
47 µF 10 µF R9
4 13 4
PWRGD LSG 4.7 Ω
5 +
12 C11
RT VBIAS
6 11 100 µF
SYNC PGND
R13 7 8 5
10 C16
110 kΩ ENA AGND
8 1 µF C14
9 3300 pF
COMP VSENSE
PWRPAD
17
C13
82 nF R6
768 Ω
Easy 1805 Out of Phase
Synchronization R12
C17
1800 pF 1 kΩ

R11
Q1, Q2: Fairchild Semiconductor FDR6674A R7 137 Ω C12
L1, L2: Vishay IHLP-5050CE 976 Ω 33 nF
C2, C11: Sanyo 6TPC100M

Figure 26. 3.3-V/1.8-V Power Supply With Sequencing

Figure 26 is an example of power supply sequencing using SYNC pin is an output. This synchronization signal is fed
two TPS54350s. U1 is used to generate an output of 3.3 to the SYNC pin of U2. The RT pin of U2 has a 110-kΩ
V, while the voltage output of U2 is set at 1.8 V, typical I/O resistor to ground, and the SYNC pin for this device acts
and core voltages for microprocessors and FPGAs. In the as an input. The 1.8-V supply operates synchronously with
circuit, the 3.3−V supply is designed to power up first. The the 3.3-V supply and their switching node rising edges are
PWRGD pin of U1 is tied to the ENA pin of U2 so that the approximately 180° out of phase allowing for a reduction
1.8-V supply starts to ramp up after the 3.3-V supply is in the input voltage ripple. See Figure 19 for this wave
within regulation. Since the RT pin of U1 is floating, the form.

20
 www.ti.com

SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

U1
TPS54350PWP C1
5V 0.1 µF L1
1 16
VIN BOOT 22 µH
R2 2 15 1 2 GND
VIN PH
+
C3 100 kΩ
C2 3 14 8 7 6 5
10 µF UVLO PH
220 µF C7
4 13
D-Case Alum R3 PWRGD LSG Q1 10 µF
43.2 kΩ 5 12 4
RT VBIAS
6 11 +
SYNC PGND C4
7 10 C5 220 µF
ENA AGND
9 1 µF D-Case Alum
C6
8
(1) COMP VSENSE 22 µF
PWRPAD 3 2 1
17 VOUT
–5 V @ 1.5 A
C9 (1) R9
2200 pF R8
130 kΩ 100 kΩ

R4 C10
C8 3.09 kΩ 470 pF
470 pF

C4: Panasonic EEVFK1A221XP R1

L1: Coilcraft DO3340P-223 21.5 kΩ
(1) Do not connect to system ground plane.
Q1: International Rectifier IRF7402
(1)

Figure 27. Inverting Power Supply, 5 V to −5 V at 1.5 A

In Figure 27 the TPS54350 is configured as an inverting output filter, which is normally the output in a buck
supply. The −5-V output is at the pins which would normally converter, is tied to ground. An additional 10-µF capacitor,
be connected to ground. The output junction of the LC C7, is required from the output to VIN.
U1
TPS54350PWP C1
0.1 µF L1
+12 V 1 16 10 µH
VIN BOOT
VOUT 5 V @ 3 A
C2 2 15
VIN PH
10 µF
16 V 3 14
UVLO PH
4 13
PWRGD LSG
5 12
RT VBIAS
6
SYNC
11 D1 C3 +
PGND
220 µF C4
R1 7 10 C5 6.3 V
ENA AGND 10 µF
80.6 kW 1 µF 6.3 V
8 9
COMP VSENSE
PWRPAD
17

C7
0.01 µF R2 R3
5.90 kΩ 4.64 kΩ

R4 C8
C9 7.50 kΩ 4700 pF
10 pF

R5
D1: On Semiconductor MBRS340T3 1 kΩ
C3: Panasonic EEVFK0J221P
L1: Coilcraft DO3316P-103

Figure 28. 12-V to 5-V Using Aluminum Electrolytic for LCD TV

Figure 28 is an example of a 12-V to 5-V converter using economical output filter components.

21

 www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

MINIMUM OUTPUT VOLTAGE MAXIMUM SWITCHING FREQUENCY MINIMUM OUTPUT VOLTAGE

vs vs vs
INPUT VOLTAGE INPUT VOLTAGE INPUT VOLTAGE
5.5 800 5.5
IO > 0.5 A VO = 2.5 V VO = 3.3 V IO = 0 A
700 kHz
5 5

Maximum Switching Frequency − kHz

700
4.5 4.5 600 kHz

Minimum Output Voltage − V

Minimum Output Voltage − V

600 4 500 kHz

4 700 kHz
3.5 600 kHz 500 3.5 400 kHz

3 500 kHz 3 300 kHz

400
2.5 2.5
400 kHz
300 VO = 1.8 V 2
2
VO = 1.5 V 1.5
1.5 200
VO = 0.9 V
1 VO = 1.2 V 1
100 0.5 200 kHz
0.5 300 kHz IO > 0.5 A
200 kHz
0 0 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VI − Input Voltage − V VI − Input Voltage − V VI − Input Voltage − V

Figure 29 Figure 30 Figure 31

RT RESISTANCE VIN(UVLO) START AND STOP

MAXIMUM SWITCHING FREQUENCY
vs vs
vs
SWITCHING FREQUENCY FREE-AIR TEMPERATURE
INPUT VOLTAGE
225 4.5
800 TJ = 25°C
VO = 1.8 V VO = 2.5 V
Maximum Switching Frequency − kHz

700 200
4.3
VO = 3.3 V

VI − Input Voltage − V
600 Start
175
RT Resistance − kW

500 4.1
150
400
125 3.9
Stop
300
100
200 3.7
VO = 0.9 V
VO = 1.2 V 75
100 VO = 1.5 V
IO < 0.1 A 3.5
50
0 −50 −25 0 25 50 75 100 125 150
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 200 300 400 500 600 700
Switching Frequency − kHz TA − Free-Air Temperature − 5C
VI − Input Voltage − V
Figure 32 Figure 33 Figure 34

ENABLED SUPPLY CURRENT DISABLED SUPPLY CURRENT BIAS VOLTAGE

vs vs vs
INPUT VOLTAGE INPUT VOLTAGE INPUT VOLTAGE
10 1.3 8.0
TJ = 25°C
TJ = 25°C
fS = 500 kHz TJ = 25°C
9 7.5
Enabled Supply Current − mA

Disabled Supply Current − mA

VBIAS − Bias Voltage − V

8 1.2 7.0

6.5
7
1.1 6.0
6
5.5
5
1.0 5.0
4
4.5

3 0.9 4.0
0 5 10 15 20 25 0 5 10 15 20 25 0 5 10 15 20 25
VI − Input Voltage − V VI − Input Voltage − V VI − Input Voltage − V
Figure 35 Figure 36 Figure 37

22
 www.ti.com

SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

POWER GOOD THRESHOLD INTERNAL VOLTAGE REFERENCE CURRENT LIMIT

vs vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE INPUT VOLTAGE
98.0 0.8912 6.0
TJ = 25°C
VIN = 12 V
PWRGD − Power Good Threshold − %

Vref − Internal Voltage Reference − V

VI = 12 V
0.8910

97.5 5.5
0.8908

Current Limit − A
0.8906
97.0 5.0
0.8904

0.8902
96.5 4.5

0.8900

96.0 0.8898 4.0

−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 5.0 7.5 10.0 12.5 15.0 17.5 20.0
TJ − Junction Temperature − 5C TJ − Junction Temperature − 5C VI − Input Voltage − V

Figure 39 Figure 40
Figure 38

ON RESISTANCE PH VOLTAGE SLOW START CAPACITANCE

vs vs vs
JUNCTION TEMPERATURE SUPPLY CURRENT TIME
150 2 0.50
VI = 12 V
IO = 0.5 A 0.45
RSS = 2 kΩ

Slow Start Capacitance − µ F

130 0.40
1.75
On Resistance − mW

0.35
PH Voltage − V

110 0.30
VI = 4.5 V
1.50 0.25

90 0.20
VI = 12 V
0.15
1.25
70 0.10

0.05

50 1 0
−50 −25 0 25 50 75 100 125 150 100 150 200 250 300 0 10 20 30 40 50 60 70 80

TJ − Junction Temperature − 5C I CC − Supply Current − mA t − Time − ms

Figure 41 Figure 42 Figure 43

POWER GOOD DELAY HICCUP TIME INTERNAL SLOW START TIME

vs vs vs
SWITCHING FREQUENCY SWITCHING FREQUENCY SWITCHING FREQUENCY
4.5 10 5

4 9 4.5

3.5
Power Good Delay − ms

8 4
Slow Start Time − ms
Hiccup Time − ms

3
7 3.5
2.5
6 3
2
5 2.5
1.5
4 2
1

0.5 3 1.5

0 2 1
250 350 450 550 650 750 250 350 450 550 650 750 250 350 450 550 650 750
Switching Frequency − kHz Switching Frequency − kHz Switching Frequency − kHz

Figure 44 Figure 45 Figure 46

23

 www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

FREE-AIR TEMPERATURE MAXIMUM OUTPUT VOLTAGE POWER DISSIPATION

vs vs vs
MAXIMUM OUTPUT CURRENT INPUT VOLTAGE FREE-AIR TEMPERATURE
140 14 2.5
TJ= 125°C

PD − Power Dissipation − W
120 12
T A − Free-Air Temperature − ° C

V O − Output Voltage − V
100 10 θJA = 42.1°C/W

80 8 1.5

60 6
1

40 4 θJA = 191.9°C/W

0.5
20 2

0 0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 25 45 65 85 105 125
I O − Output Current − A V I − Input Voltage − V TA − Free-Air Temperature − °C

Figure 47 Figure 48 Figure 49

24
 www.ti.com

SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004

THERMAL PAD MECHANICAL DATA

PWP (R−PDSO−G16) PowerPADt PLASTIC SMALL−OUTLINE

PPTD024

25
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54350PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 PS54350

TPS54350PWPG4 ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 PS54350

TPS54350PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 PS54350

TPS54350PWPRG4 ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 150 PS54350

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54350 :

• Enhanced Product : TPS54350-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54350PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54350PWPR HTSSOP PWP 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54350PWP PWP HTSSOP 16 90 530 10.2 3600 3.5
TPS54350PWP PWP HTSSOP 16 90 530 10.2 3600 3.5
TPS54350PWPG4 PWP HTSSOP 16 90 530 10.2 3600 3.5
TPS54350PWPG4 PWP HTSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PWP0016C SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
AREA 14X 0.65 SEATING
16 PLANE
1

2X
5.1
4.55
4.9
NOTE 3

8
9
0.30
4.5 16X
B 0.19
4.3
0.1 C A B
SEE DETAIL A

(0.15) TYP

2X 0.95 MAX
NOTE 5 4X (0.3)
8 9
2X 0.23 MAX
NOTE 5

2.31 17
0.25
1.75
GAGE PLANE 1.2 MAX

0.75 0.15
1 16 0 -8 0.50 0.05
DETAIL A
A 20

THERMAL 2.46 TYPICAL

PAD 1.75

4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
(2.46)
16X (1.5)
SYMM METAL COVERED
BY SOLDER MASK
1
16X (0.45) 16 (1.2) TYP

(R0.05) TYP

SYMM 17 (2.31)
(5)
(0.6) NOTE 9
14X (0.65)

( 0.2) TYP
VIA 8 9

SOLDER MASK (1) TYP

DEFINED PAD SEE DETAILS
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4224559/B 01/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.46)
BASED ON
16X (1.5) METAL COVERED
0.125 THICK
STENCIL BY SOLDER MASK
1
16X (0.45) 16

(R0.05) TYP

(2.31)
SYMM 17 BASED ON
0.125 THICK
STENCIL
14X (0.65)

8 9

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 2.58
0.125 2.46 X 2.31 (SHOWN)
0.15 2.25 X 2.11
0.175 2.08 X 1.95

4224559/B 01/2019
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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